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1. 发明授权

US5440514A Write control for a memory using a delay locked loop 失效
标题翻译：使用延迟锁定环对内存进行写入控制
公开(公告)号：US5440514A
公开(公告)日：1995-08-08
申请号：US207510
申请日：1994-03-08
申请人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
发明人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
IPC分类号： G11C7/22 , G11C17/10
CPC分类号： G11C7/222 , G11C7/22
摘要： A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.
摘要翻译：存储器（20）包括用于控制存储器（20）的写周期的写控制延迟锁定环（52）。延迟锁定环（52）包括仲裁电路（264），电压控制延迟（VCD）电路（260）和VCD控制电路（265）。仲裁器电路（264）将时钟信号与来自VCD电路（260）的延迟的时钟信号进行比较。作为响应，仲裁器电路（264）向VCD控制电路（265）提供延迟信号。 VCD控制电路（265）接收延迟信号并调整延迟的时钟信号的传播延迟以补偿时钟频率的变化，以及补偿处理，温度和电源变化。

2. 发明授权

US5402389A Synchronous memory having parallel output data paths 失效
标题翻译：具有并行输出数据路径的同步存储器
公开(公告)号：US5402389A
公开(公告)日：1995-03-28
申请号：US207513
申请日：1994-03-08
申请人： Stephen T. Flannagan , Kenneth W. Jones , Roger I. Kung
发明人： Stephen T. Flannagan , Kenneth W. Jones , Roger I. Kung
IPC分类号： G11C11/413 , G11C7/10 , G11C8/00
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A synchronous memory (20) has parallel data output registers (34) and a dummy path (46). The output data from a memory array (22) is provided to the parallel output registers (34). The output registers (34) provide two parallel, interleaved, output data paths. The data in each path changes every other cycle of a clock signal. Dummy path (46) contains delay elements that model a propagation delay for a data path of the memory (20) during a read cycle. Using parallel data output registers (34) increases a time in which data is valid during the read cycle. The dummy path (46) tracks the output data signal in terms of process, power supply and temperature variations to ensure that the correct data is acquired during the read cycle.
摘要翻译：同步存储器（20）具有并行数据输出寄存器（34）和虚拟路径（46）。来自存储器阵列（22）的输出数据被提供给并行输出寄存器（34）。输出寄存器（34）提供两个并行的交错输出数据路径。每个路径中的数据改变时钟信号的每隔一个周期。虚拟路径（46）包含在读周期期间对存储器（20）的数据路径建立传播延迟的延迟元件。使用并行数据输出寄存器（34）会增加读取周期数据有效的时间。伪路径（46）根据过程，电源和温度变化跟踪输出数据信号，以确保在读取周期期间获取正确的数据。

3. 发明授权

US5256917A ECL logic gate with voltage protection 失效
标题翻译： ECL逻辑门电压保护
公开(公告)号：US5256917A
公开(公告)日：1993-10-26
申请号：US863623
申请日：1992-04-03
申请人： Stephen T. Flannagan , John D. Porter
发明人： Stephen T. Flannagan , John D. Porter
IPC分类号： H03K19/003 , H03K19/086 , H03K19/0175
CPC分类号： H03K19/086 , H03K19/00307
摘要： An ECL logic gate (70) includes a voltage protection clamp (60) for protecting a first bipolar transistor (58) from being too heavily reverse biased when an input signal A.sub.IN is pulled to V.sub.SS. The ECL logic gate (70) includes an emitter-follower input stage and a differential amplifier stage. A voltage protection clamp (60) includes a second transistor (52) and a resistor (53) and acts to divide the amount of reverse bias on the first bipolar transistor (58) between a third transistor (51) and the first transistor (58), thereby bringing the reverse bias voltage on the first transistor (58) within acceptable levels to prevent degradation of the first transistor (58).
摘要翻译： ECL逻辑门（70）包括电压保护钳位（60），用于当输入信号AIN被拉到VSS时，用于保护第一双极晶体管（58）不被过大的反向偏置。 ECL逻辑门（70）包括射极跟随器输入级和差分放大级。电压保护夹具（60）包括第二晶体管（52）和电阻器（53），并且用于将第一晶体管（51）和第一晶体管（58）之间的第一双极晶体管（58）上的反向偏置量），从而使第一晶体管（58）上的反向偏置电压达到可接受的水平以防止第一晶体管（58）的劣化。

4. 发明授权

US5059829A Logic level shifting circuit with minimal delay 失效
标题翻译：具有最小延迟的逻辑电平移位电路
公开(公告)号：US5059829A
公开(公告)日：1991-10-22
申请号：US577178
申请日：1990-09-04
申请人： Stephen T. Flannagan , Tai-Sheng Feng
发明人： Stephen T. Flannagan , Tai-Sheng Feng
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0175
CPC分类号： H03K19/0016 , H03K19/0136 , H03K19/017527
摘要： A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.
摘要翻译：能够转换一组ECL和一组CMOS逻辑电平的电路具有差分放大器，两个发射极跟随器，电流切换电路和电平移位电路。差分放大器为使用ECL电压电平非常快速地切换的两个发射极跟随器提供了一个共模输入。通过在逻辑高电压到低电压瞬变期间提供松弛电流来实现高运行速度。电流开关电路通过在逻辑低电平至高瞬态期间关断松弛电流来节省功耗，在此期间发射极跟随器足够快地切换。电平移位电路将ECL逻辑电压电平的集合转换为一组CMOS电压电平，并且CMOS输出电压用于控制电流开关电路而不引入开关延迟时间。

5. 发明授权

US5043602A High speed logic circuit with reduced quiescent current 失效
标题翻译：具有降低静态电流的高速逻辑电路
公开(公告)号：US5043602A
公开(公告)日：1991-08-27
申请号：US498530
申请日：1990-03-26
申请人： Stephen T. Flannagan
发明人： Stephen T. Flannagan
IPC分类号： H03K19/01 , H03K17/042 , H03K17/66 , H03K19/00 , H03K19/08 , H03K19/086
CPC分类号： H03K17/04213 , H03K17/667 , H03K19/001
摘要： A high speed logic circuit with reduced quiescent current receives a plurality of input signals and performs a predetermined logic operation on the plurality of input signals. The predetermined logic operation may be, for example, a comparison of true and complement input signals, or a logical AND of two input signals. In response to the predetermined logic operation, first and second bipolar transistors coupled between first and second power supply voltage terminals are alternately made conductive to provide an output signal therebetween at ECL levels. A biasing portion ensures a proper voltage on a base of the second bipolar transistor. A current portion draws current from the base of the second bipolar transistor until the voltage of the output signal reaches a logic low voltage, and then makes the second transistor nonconductive, keeping the quiescent current of the circuit to a minimum.
摘要翻译：具有降低的静态电流的高速逻辑电路接收多个输入信号并对多个输入信号执行预定的逻辑运算。预定的逻辑运算可以是例如真和补输入信号的比较，或两个输入信号的逻辑与。响应于预定的逻辑操作，耦合在第一和第二电源电压端子之间的第一和第二双极晶体管交替地导通，以在ECL电平之间提供输出信号。偏置部分确保在第二双极晶体管的基极上的适当电压。电流部分从第二双极晶体管的基极吸取电流，直到输出信号的电压达到逻辑低电压，然后使第二晶体管不导通，使电路的静态电流保持最小。

6. 发明授权

US4928268A Memory using distributed data line loading 失效
标题翻译：内存使用分布式数据线加载
公开(公告)号：US4928268A
公开(公告)日：1990-05-22
申请号：US342160
申请日：1989-04-21
申请人： Scott G. Nogle , Perry H. Pelley, III , Stephen T. Flannagan , Bruce E. Engles
发明人： Scott G. Nogle , Perry H. Pelley, III , Stephen T. Flannagan , Bruce E. Engles
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/417
CPC分类号： G11C7/1048
摘要： A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.

7. 发明授权

US4698788A Memory architecture with sub-arrays 失效
标题翻译：具有子阵列的内存架构
公开(公告)号：US4698788A
公开(公告)日：1987-10-06
申请号：US750637
申请日：1985-07-01
申请人： Stephen T. Flannagan , Paul A. Reed , John Barnes
发明人： Stephen T. Flannagan , Paul A. Reed , John Barnes
IPC分类号： G11C11/413 , G11C8/12 , G11C8/14 , G11C11/41 , G11C13/00
CPC分类号： G11C8/14 , G11C8/12
摘要： A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders. The static RAM has an architecture characterized by the memory having a top side, a bottom side, a left side, and a right side; the rows of sub-arrays running from left to right, and sequentially numbered from left to right with the first column of sub-arrays being nearest the top side; the columns of sub-arrays running from top to bottom, and sequentially numbered from top to bottom with the first row sub-arrays being nearest the left side; and the plurality of sense amplifiers being interposed in the rows of sub-arrays and located between the columns of sub-arrays.
摘要翻译：静态RAM具有排列成行和列的多个子阵列，每个子阵列具有从上到下方向延伸子阵列的长度的字线，并且具有运行子阵列的宽度的位线并且具有用于响应于接收到对应于所选择的字线的行选择信号而启用所选字线的字线驱动器; 全球行解码器，用于提供由行地址信号确定的行选择信号; 第一多个列预解码器，用于对提供在第一行子阵列的位线上的数据执行部分解码，每个列预解码器对应于特定子阵列; 第二多个列预解码器，用于对提供在子阵列的第二行的位线上的数据执行部分解码，每个列预解码器对应于特定的子阵列; 以及用于感测第一和第二列解码器的输出的多个读出放大器。该静态RAM具有以下结构，其特征在于，具有上侧，底侧，左侧和右侧的存储器; 子列的行从左到右，从左到右顺序编号，第一列子列最靠近顶面; 子列的列从上到下运行，并且从上到下依次编号，第一行子阵列最靠近左侧; 并且多个读出放大器插入在子阵列中并位于子阵列之间。

8. 发明授权

US4661931A Asynchronous row and column control 失效
标题翻译：异步行和列控制
公开(公告)号：US4661931A
公开(公告)日：1987-04-28
申请号：US762341
申请日：1985-08-05
申请人： Stephen T. Flannagan , Paul A. Reed
发明人： Stephen T. Flannagan , Paul A. Reed
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C8/00 , G11C8/18 , G11C11/34 , G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C8/18
摘要： A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. In response to being selected, a bit line is coupled to a data line. In response to a column address transition, all of the bit lines are decoupled from the data lines while bit lines are precharged. In response to a row address transition, the word lines are disabled while the bit lines are equilibrated.
摘要翻译：存储电路具有多个位线对和与每个这样的交叉点处的存储单元相交的字线。列地址选择要访问的位线，行地址选择启用的字线。响应于被选择，位线被耦合到数据线。响应于列地址转换，所有位线都与数据线去耦，而位线被预充电。响应于行地址转换，字线在位线平衡时被禁止。

9. 发明授权

US4636991A Summation of address transition signals 失效
标题翻译：地址转换信号的求和
公开(公告)号：US4636991A
公开(公告)日：1987-01-13
申请号：US766616
申请日：1985-08-16
申请人： Stephen T. Flannagan , Paul A. Reed
发明人： Stephen T. Flannagan , Paul A. Reed
IPC分类号： G11C11/41 , G11C8/00 , G11C8/18 , G11C11/413
CPC分类号： G11C8/18
摘要： A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
摘要翻译：存储器电路在使用地址转换检测来平衡位线时，产生用于行地址的求和地址转换信号以及列地址的求和地址转换信号。每个地址信号都有一个转换检测器。用于行地址信号的转移检测器的输出在至少两个逻辑级中相加使用CMOS逻辑门来产生行地址的求和地址信号。类似地，用于列地址信号的转移检测器的输出在至少两个逻辑级中相加使用CMOS逻辑门来产生列地址的求和地址信号。

10. 发明授权

US6157583A Integrated circuit memory having a fuse detect circuit and method therefor 有权
标题翻译：具有熔丝检测电路的集成电路存储器及其方法
公开(公告)号：US6157583A
公开(公告)日：2000-12-05
申请号：US261876
申请日：1999-03-02
申请人： Glenn E. Starnes , Stephen T. Flannagan , Ray Chang
发明人： Glenn E. Starnes , Stephen T. Flannagan , Ray Chang
IPC分类号： H01L21/82 , G06F11/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号： G11C29/02 , G06F11/006 , G11C29/44
摘要： Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.
摘要翻译：集成电路存储器（100）中的保险丝和检测电路（124）包括用于检测保险丝（208）的开路状态或闭路状态的铜熔丝（208）和熔丝状态检测级（202）。保险丝检测电路（124）提供对应于熔丝状态的输出信号，并且在检测期间，将熔丝两端的电压降限制为与施加到集成电路存储器的电源电压无关的绝对值。保险丝检测电路（124）在集成电路存储器（100）上电时工作，并且在保险丝的状态被检测和锁存之后被禁用，并且电源足以用于集成电路存储器（100）的可靠运行，。通过限制熔断的铜熔丝（208）上的电压降，潜在的电迁移问题就会降低。

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