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1. 发明授权

US11952169B2 Collapsible storage container 有权
公开(公告)号：US11952169B2
公开(公告)日：2024-04-09
申请号：US18311969
申请日：2023-05-04
申请人： Stephen A. Smith
发明人： Stephen A. Smith
IPC分类号： B65D21/08 , A47J47/12 , B65D8/00 , B65D81/20 , B65D85/36
CPC分类号： B65D21/086 , A47J47/12 , B65D11/02 , B65D81/20 , B65D85/36 , B65D2205/00
摘要： Various aspects of the disclosure generally relate to a collapsible storage container with multiple sleeves. In some implementations a two-sleeve variant is described. In some implementations a three-sleeve variant is described. Both variants may be used to contain appropriately sized and shaped objects, for example bread, maps, posters, blueprints, plans, etc.

2. 发明申请

US20230008715A1 Collapsible Storage Container 有权
公开(公告)号：US20230008715A1
公开(公告)日：2023-01-12
申请号：US17369038
申请日：2021-07-07
申请人： Stephen A. Smith
发明人： Stephen A. Smith
IPC分类号： B65D21/08 , B65D85/36 , A47J47/12 , B65D8/00 , B65D81/20
摘要： Various aspects of the disclosure generally relate to a collapsible storage container with multiple sleeves. In some implementations a two-sleeve variant is described. In some implementations a three-sleeve variant is described. Both variants may be used to contain appropriately sized and shaped objects, for example bread, maps, posters, blueprints, plans, etc.

3. 外观设计

USD487669S1 Ergonomic disposable plate sidewall 失效
标题翻译：符合人体工学的一次性板材侧壁
公开(公告)号：USD487669S1
公开(公告)日：2004-03-23
申请号：US29182704
申请日：2003-05-30
申请人： Stephen A. Smith , Warren Giles Wiedmeyer , John Stewart Gitschlag , James Tam Joines, Jr. , Kimberly Vaile Healy , Bryce G. Rutter , John Howard Loudenslager , Brian C. Bone , Jan R. Stillerman
设计人： Stephen A. Smith , Warren Giles Wiedmeyer , John Stewart Gitschlag , James Tam Joines, Jr. , Kimberly Vaile Healy , Bryce G. Rutter , John Howard Loudenslager , Brian C. Bone , Jan R. Stillerman

4. 发明授权

US5812858A Method and apparatus for providing register and interrupt compatibility between non-identical integrated circuits 失效
标题翻译：用于在不相同集成电路之间提供寄存器和中断兼容性的方法和装置
公开(公告)号：US5812858A
公开(公告)日：1998-09-22
申请号：US719596
申请日：1996-09-25
申请人： Narasimha R. Nookala , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Jihad Y. Abudayyeh , Arunachalam Vaidyanathan
发明人： Narasimha R. Nookala , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Jihad Y. Abudayyeh , Arunachalam Vaidyanathan
IPC分类号： G06F9/30 , G06F9/318 , G06F13/10 , G06F9/46
CPC分类号： G06F13/105 , G06F9/30098 , G06F9/30123 , G06F9/30189 , G06F9/455
摘要： An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode the interrupt information is written to an appropriate register and then mapped into the appropriate bits of the physical register set. In the second mode the interrupt information is written directly to the appropriate register. In both the first and second modes, steering bits from the appropriate register are used to map system, management and wakeup interrupts to the appropriate interrupt pad where the interrupt request signal is then shaped.
摘要翻译：用于在具有不同寄存器和中断配置的集成电路之间提供寄存器兼容性的设备被设计为使用为先前硬件编写的软件进行操作。为先前硬件编写的软件版本尝试非本地寄存器访问，集成电路设计用于模拟非本地寄存器集。针对当前硬件专门编写的软件版本会尝试不需要仿真的本地寄存器访问。在优选实施例中，集成电路中仅包括一个物理寄存器组，并且当尝试非本地寄存器访问时使用兼容性引擎。兼容性引擎耦合在总线接口单元和物理寄存器组之间，并且允许用户或系统设计者寻址具有与物理寄存器组不同的配置的另一个集成电路的寄存器组。兼容性引擎转换地址，并将仿真寄存器的数据位映射到物理寄存器集中的寄存器。或者，集成电路可以物理地包括两组寄存器。中断兼容性电路还被设计为在至少第一模式或第二模式中操作。在第一种模式下，中断信息被写入适当的寄存器，然后映射到物理寄存器组的相应位。在第二种模式下，中断信息直接写入适当的寄存器。在第一和第二模式中，来自适当寄存器的转向位用于将系统，管理和唤醒中断映射到中断请求信号然后成形的适当中断焊盘。

5. 发明授权

US5796981A Method and apparatus for providing register compatibility between non-identical integrated circuits 失效
标题翻译：用于在不相同的集成电路之间提供寄存器兼容性的方法和装置
公开(公告)号：US5796981A
公开(公告)日：1998-08-18
申请号：US308167
申请日：1994-09-16
申请人： Jihad Y. Abudayyeh , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Arunachalam Vaidyanathan
发明人： Jihad Y. Abudayyeh , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Arunachalam Vaidyanathan
IPC分类号： G06F9/30 , G06F9/318 , G06F9/00 , G06F13/00
CPC分类号： G06F9/30174 , G06F9/30138
摘要： An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.
摘要翻译：用于在具有不同寄存器和中断配置的集成电路之间提供寄存器兼容性的装置被设计为与软件一起操作。软件可以尝试非本地寄存器访问; 本发明的集成电路将模拟非本地寄存器组。在优选实施例中，集成电路中仅包括一个物理寄存器组，并且当尝试非本地寄存器访问时使用兼容性引擎。兼容性引擎耦合在总线接口单元和物理寄存器组之间，并且允许用户或系统设计者寻址具有与物理寄存器组不同的配置的另一个集成电路的寄存器组。兼容性引擎转换地址，并将仿真寄存器的数据位映射到物理寄存器集中的寄存器。或者，集成电路可以物理地包括两组寄存器。中断兼容性电路还被设计为在至少第一模式或第二模式中操作。在第一种模式下，将中断信息写入适当的寄存器，然后映射到物理寄存器组的相应位。在第二种模式下，中断信息直接写入适当的寄存器。

6. 发明授权

US5727184A Method and apparatus for interfacing between peripherals of multiple formats and a single system bus 失效
公开(公告)号：US5727184A
公开(公告)日：1998-03-10
申请号：US266975
申请日：1994-06-27
申请人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
发明人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
IPC分类号： G06F13/38 , G06F13/10 , G06F5/01
CPC分类号： G06F13/385
摘要： A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.

7. 发明授权

US5724529A Computer system with multiple PC card controllers and a method of controlling I/O transfers in the system 失效
标题翻译：具有多个PC卡控制器的计算机系统和一种控制系统中I / O传输的方法
公开(公告)号：US5724529A
公开(公告)日：1998-03-03
申请号：US561777
申请日：1995-11-22
申请人： Stephen A. Smith , Jafar Naji
发明人： Stephen A. Smith , Jafar Naji
IPC分类号： G06F13/14 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers. The index registers of the PC card controllers are updated when the processor writes to an I/O address, without acknowledging the write on the PCI bus. This allows the writes to propagate through the system to lower levels, instead of being stopped by a subtractive decode device. To perform this, each PC card controller compares the socket pointer information with the updated index in the index register. When at least a portion of the socket pointer information matches at least a portion of the updated index, the PC card controller updates with write data the data register pointed to by the index register.
摘要翻译：用于控制计算机系统中的输入/输出（I / O）操作的方法和装置提供多个PC卡控制器，但允许使用旧的软件。 PCI总线耦合到中央处理单元，并且ISA总线通过桥耦合到PCI总线。至少一个PC卡控制器耦合到PCI总线，并且至少一个其它PC卡控制器耦合到ISA总线。每个PC卡控制器具有至少一个插座，其中设备可连接，每个插座可由处理器在通过PC卡控制器的I / O地址单独寻址。每个控制器还具有套接字指针寄存器，每个套接字指针寄存器可以使用套接字指针信息进行加载，该指针信息在计算机系统中的多个控制器的所有插座中唯一地标识控制器的每个套接字。每个控制器还具有索引寄存器和多个数据寄存器，存储在索引寄存器中的索引指向数据寄存器之一。当处理器写入I / O地址时，PC卡控制器的索引寄存器被更新，而不会确认PCI总线上的写入。这允许写入通过系统传播到较低的电平，而不是被减法解码设备停止。为了执行此操作，每个PC卡控制器将套接字指针信息与索引寄存器中更新的索引进行比较。当插座指针信息的至少一部分与更新的索引的至少一部分匹配时，PC卡控制器用写入数据更新由索引寄存器指向的数据寄存器。

8. 外观设计

USD379587S Base for a food container 失效
公开(公告)号：USD379587S
公开(公告)日：1997-06-03
申请号：US46468
申请日：1995-11-15
申请人： Timothy S. Goins , Stephen A. Smith , Matthew O. Banach , Daniel R. Proper
设计人： Timothy S. Goins , Stephen A. Smith , Matthew O. Banach , Daniel R. Proper

9. 发明授权

US5518133A Packaging tab 失效
标题翻译：包装标签
公开(公告)号：US5518133A
公开(公告)日：1996-05-21
申请号：US385711
申请日：1995-02-08
申请人： Thomas J. Hayes , Stephen A. Smith
发明人： Thomas J. Hayes , Stephen A. Smith
IPC分类号： B65D17/34 , B65D43/02
CPC分类号： B65D43/0212 , B65D2543/00092 , B65D2543/00296 , B65D2543/00351 , B65D2543/00527 , B65D2543/00537 , B65D2543/00657 , B65D2543/00685 , B65D2543/00731 , B65D2543/00796 , B65D2543/00842
摘要： A cover for a packaging arrangement, comprising a side flange having an undercut disposed therein for releasably engaging a base of said packaging arrangement; and a non-planar shaped tab having a first edge connected to said side flange along the length of said first edge and having a second edge connected to said side flange only at the terminating points of said second edge, said undercut extending in a continuous, unbroken manner in the vicinity of said tab.
摘要翻译：一种用于包装装置的盖子，包括一个侧面凸缘，该侧面凸缘具有设置在其中的底切部，用于可释放地接合所述包装装置的底座; 以及非平面形突片，其具有沿着所述第一边缘的长度连接到所述侧凸缘的第一边缘，并且具有仅在所述第二边缘的终止点处连接到所述侧凸缘的第二边缘，所述底切部以连续的，不间断地在所述突片附近。

10. 发明授权

US5269430A Individual serving food container with improved housing and closure arrangement 失效
标题翻译：个人服务食物容器，改善住房和关闭安排
公开(公告)号：US5269430A
公开(公告)日：1993-12-14
申请号：US826895
申请日：1992-01-28
申请人： Robert S. Schlaupitz , Patricia A. Antoni , Stephen A. Smith
发明人： Robert S. Schlaupitz , Patricia A. Antoni , Stephen A. Smith
IPC分类号： B65D43/16 , B65D6/00
CPC分类号： B65D43/162 , B65D2251/105 , Y10S206/815
摘要： An individual serving food container is provided for housing individual servings of food products, such as pie slices and the like, which are generally triangular or wedge shaped and have an outwardly extending "crust" portion. The container includes a tray/cover combination having means for supporting the crust portions of such food product servings from collapsing when housed within the container. The rear wall of the tray has a transverse edge thereof remote from the bottom wall which extends rearwardly therefrom to define a platform adapted to support the outwardly extending crust portion of the wedge-shaped food serving contained in the housing cavity. The container is also provided with means facilitating removal of stored individual servings therefrom and guide means for facilitating proper alignment of locking elements disposed on the cover and tray so as to simplify the locking operation.
摘要翻译：提供个人服务的食物容器用于容纳通常为三角形或楔形并且具有向外延伸的“外壳”部分的食品的各种食品，例如馅饼片等。容器包括托盘/盖组合件，其具有用于支撑这种食品产品的外皮部分在容纳在容器内时不会塌陷的装置。托盘的后壁具有远离底壁的横向边缘，其从其向后延伸以限定适于支撑容纳在壳体腔中的楔形食品的向外延伸的外壳部分的平台。容器还设置有便于从其中取出存储的各个部件的装置和用于促进布置在盖和托盘上的锁定元件的适当对准的引导装置，以简化锁定操作。

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