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1. 发明授权

US5860016A Arrangement, system, and method for automatic remapping of frame buffers when switching operating modes 失效
标题翻译：切换操作模式时自动重新映射帧缓冲区的布置，系统和方法
公开(公告)号：US5860016A
公开(公告)日：1999-01-12
申请号：US720392
申请日：1996-09-30
申请人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
发明人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
IPC分类号： G09G3/20 , G09G3/36 , G06F1/32
CPC分类号： G09G3/3611 , G09G2330/022 , G09G2340/0428 , G09G3/20
摘要： An arrangement, system, and method to allow a computer system to have a normal operating mode with full display capability and a low-power operating mode with reduced display capability is provided. The computer system automatically switches to the low-power operating mode from the normal operating mode following a programmable period of inactivity. While display data is retrieved from an external DRAM in the normal operating mode, display data is retrieved from an internal SRAM in the low-power operating mode. The computer system switches back to the normal operating mode when one of the predetermined activities is detected.
摘要翻译：提供了允许计算机系统具有全显示能力的正常操作模式和具有降低的显示能力的低功率操作模式的布置，系统和方法。计算机系统在可编程的不活动时间段后，从正常操作模式自动切换到低功耗工作模式。当在正常操作模式下从外部DRAM检索显示数据时，在低功率操作模式下从内部SRAM检索显示数据。当检测到预定活动之一时，计算机系统切换回正常操作模式。

2. 发明授权

US5923895A Method and arrangement to effectively retrieve residual data from a buffer 失效
标题翻译：有效地从缓冲器中检索残留数据的方法和装置
公开(公告)号：US5923895A
公开(公告)日：1999-07-13
申请号：US751188
申请日：1996-11-15
申请人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
发明人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
IPC分类号： G06F5/06 , G06F13/00 , G11C7/00
CPC分类号： G06F5/06
摘要： A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.
摘要翻译：提供了一种有效检索从串行数据源接收的残留数据的机制。当移位寄存器从串行数据源接收串行数据时，监视移位寄存器的活动和内容。设置状态位以反映活动和内容。这些状态位用于确定移位寄存器是否包含残差数据，并且是否应该忽略这样的残差数据，将从串行数据源接收的串行数据输出到目的地。

3. 发明授权

US5878257A Self-booting mechanism to allow dynamic system configuration and diagnostic 失效
标题翻译：自启动机制允许动态系统配置和诊断
公开(公告)号：US5878257A
公开(公告)日：1999-03-02
申请号：US749876
申请日：1996-11-15
申请人： Narasimha R. Nookala , Kameswaran Sivamani , Otto Sponring
发明人： Narasimha R. Nookala , Kameswaran Sivamani , Otto Sponring
IPC分类号： G06F9/06 , G06F9/44 , G06F9/445 , C06F9/06
CPC分类号： G06F9/4411
摘要： A mechanism to allow dynamic configurations and/or diagnostic of a computer system from a remote location is provided. The computer system receives instruction codes of a program from a data source. When executed by the CPU, the instruction codes performs the necessary erase and program operations to embed a firmware program onto to the flash memory. The firmware program can be used for configurations or diagnostic purpose.
摘要翻译：提供了允许来自远程位置的计算机系统的动态配置和/或诊断的机制。计算机系统从数据源接收程序的指令代码。当CPU执行时，指令代码执行必要的擦除和程序操作，以将固件程序嵌入闪存。固件程序可用于配置或诊断目的。

4. 发明授权

US6014717A PCMCIA host adapter and method for variable data transfers 失效
标题翻译： PCMCIA主机适配器和可变数据传输方法
公开(公告)号：US6014717A
公开(公告)日：2000-01-11
申请号：US801645
申请日：1997-02-18
申请人： Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Puducode S. Narayanan , Ashutosh S. Dikshit
发明人： Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Puducode S. Narayanan , Ashutosh S. Dikshit
IPC分类号： G06F13/28 , G06F13/40 , G06F13/16 , G06F13/36
CPC分类号： G06F13/4068 , G06F13/28
摘要： A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus. If the system bus does not have DMA capability then the DMA controller and the bus master work to disable the CPU and take control of the system bus during a DMA data transfer. The DMA controller then controls the transfer of data between the peripheral and the internal system memory.
摘要翻译： PCMCIA主机适配器包括掌握非DMA系统总线并控制DMA能力外设与内部系统存储器之间的DMA数据传输的功能。外设可以通过插入PCMCIA扩展槽的PCMCIA卡耦合到系统。通过PCMCIA总线耦合到PCMCIA扩展槽的DMA控制器控制内部系统存储器和外设之间的DMA传输。总线主控器在DMA数据传输期间禁用CPU并控制系统总线。在替代实施例中，PCMCIA主机适配器可以与具有具有DMA能力的系统总线的系统或具有不具有DMA能力的系统总线的系统一起使用。在该替代实施例中，如果系统总线具有DMA能力，则PCMCIA主机适配器有效地在外围设备和系统总线之间传递DMA信号。如果系统总线不具有DMA能力，则DMA控制器和总线主机可以在DMA数据传输期间禁用CPU并控制系统总线。然后，DMA控制器控制外设和内部系统存储器之间的数据传输。

5. 发明授权

US5812858A Method and apparatus for providing register and interrupt compatibility between non-identical integrated circuits 失效
标题翻译：用于在不相同集成电路之间提供寄存器和中断兼容性的方法和装置
公开(公告)号：US5812858A
公开(公告)日：1998-09-22
申请号：US719596
申请日：1996-09-25
申请人： Narasimha R. Nookala , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Jihad Y. Abudayyeh , Arunachalam Vaidyanathan
发明人： Narasimha R. Nookala , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Jihad Y. Abudayyeh , Arunachalam Vaidyanathan
IPC分类号： G06F9/30 , G06F9/318 , G06F13/10 , G06F9/46
CPC分类号： G06F13/105 , G06F9/30098 , G06F9/30123 , G06F9/30189 , G06F9/455
摘要： An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode the interrupt information is written to an appropriate register and then mapped into the appropriate bits of the physical register set. In the second mode the interrupt information is written directly to the appropriate register. In both the first and second modes, steering bits from the appropriate register are used to map system, management and wakeup interrupts to the appropriate interrupt pad where the interrupt request signal is then shaped.
摘要翻译：用于在具有不同寄存器和中断配置的集成电路之间提供寄存器兼容性的设备被设计为使用为先前硬件编写的软件进行操作。为先前硬件编写的软件版本尝试非本地寄存器访问，集成电路设计用于模拟非本地寄存器集。针对当前硬件专门编写的软件版本会尝试不需要仿真的本地寄存器访问。在优选实施例中，集成电路中仅包括一个物理寄存器组，并且当尝试非本地寄存器访问时使用兼容性引擎。兼容性引擎耦合在总线接口单元和物理寄存器组之间，并且允许用户或系统设计者寻址具有与物理寄存器组不同的配置的另一个集成电路的寄存器组。兼容性引擎转换地址，并将仿真寄存器的数据位映射到物理寄存器集中的寄存器。或者，集成电路可以物理地包括两组寄存器。中断兼容性电路还被设计为在至少第一模式或第二模式中操作。在第一种模式下，中断信息被写入适当的寄存器，然后映射到物理寄存器组的相应位。在第二种模式下，中断信息直接写入适当的寄存器。在第一和第二模式中，来自适当寄存器的转向位用于将系统，管理和唤醒中断映射到中断请求信号然后成形的适当中断焊盘。

6. 发明授权

US5796981A Method and apparatus for providing register compatibility between non-identical integrated circuits 失效
标题翻译：用于在不相同的集成电路之间提供寄存器兼容性的方法和装置
公开(公告)号：US5796981A
公开(公告)日：1998-08-18
申请号：US308167
申请日：1994-09-16
申请人： Jihad Y. Abudayyeh , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Arunachalam Vaidyanathan
发明人： Jihad Y. Abudayyeh , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Arunachalam Vaidyanathan
IPC分类号： G06F9/30 , G06F9/318 , G06F9/00 , G06F13/00
CPC分类号： G06F9/30174 , G06F9/30138
摘要： An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.
摘要翻译：用于在具有不同寄存器和中断配置的集成电路之间提供寄存器兼容性的装置被设计为与软件一起操作。软件可以尝试非本地寄存器访问; 本发明的集成电路将模拟非本地寄存器组。在优选实施例中，集成电路中仅包括一个物理寄存器组，并且当尝试非本地寄存器访问时使用兼容性引擎。兼容性引擎耦合在总线接口单元和物理寄存器组之间，并且允许用户或系统设计者寻址具有与物理寄存器组不同的配置的另一个集成电路的寄存器组。兼容性引擎转换地址，并将仿真寄存器的数据位映射到物理寄存器集中的寄存器。或者，集成电路可以物理地包括两组寄存器。中断兼容性电路还被设计为在至少第一模式或第二模式中操作。在第一种模式下，将中断信息写入适当的寄存器，然后映射到物理寄存器组的相应位。在第二种模式下，中断信息直接写入适当的寄存器。

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