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1. 发明授权

US5727184A Method and apparatus for interfacing between peripherals of multiple formats and a single system bus 失效
公开(公告)号：US5727184A
公开(公告)日：1998-03-10
申请号：US266975
申请日：1994-06-27
申请人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
发明人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
IPC分类号： G06F13/38 , G06F13/10 , G06F5/01
CPC分类号： G06F13/385
摘要： A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.

2. 发明授权

US5905885A Method and apparatus for interfacing between peripherals of multiple formats and a single system bus 失效
标题翻译：用于连接多种格式的外围设备和单个系统总线的方法和装置
公开(公告)号：US5905885A
公开(公告)日：1999-05-18
申请号：US933884
申请日：1997-09-19
申请人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
发明人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
IPC分类号： G06F13/38 , G06F13/10 , G06F5/01
CPC分类号： G06F13/385
摘要： A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.
摘要翻译：被称为系统适配器和插座控制器的包括一对集成电路的外围接口系统和设备使用称为窗口 - 芯片间通信协议的通信协议来接口诸如PCMCIA卡或红外线设备和具有CPU系统总线的具有不同格式的其他子系统。系统适配器使用ATA通信标准与硬盘驱动器子系统进行通信，以将ATA硬盘驱动器与CPU系统总线进行接口。与PCMCIA外设卡和IR外围设备通信的系统适配器和插座控制器之间的通信使用可与其他通信协议共享硬件资源的窗口 - 芯片间通信协议实现。系统适配器和硬盘驱动器之间以及系统适配器和插座控制器之间的通信可以提供在标准40信号带状电缆的同一链上。备选地，扩展板和插座控制器之间的通信可以与具有不同信号线格式的硬盘驱动器分离的电缆进行。系统适配器可以包括在可以连接到主板和CPU系统总线的单个接口扩展板中，或者可以直接连接或焊接到主板，并使用一个或多个总线与插座控制器和ATA硬盘驱动器进行通信。

3. 发明授权

US5794014A Method and apparatus for interfacing between peripherals of multiple formats and a single system bus 失效
标题翻译：用于连接多种格式的外围设备和单个系统总线的方法和装置
公开(公告)号：US5794014A
公开(公告)日：1998-08-11
申请号：US872330
申请日：1997-06-10
申请人： Suhas Anand Shetty , Daniel G. Bezzant
发明人： Suhas Anand Shetty , Daniel G. Bezzant
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/385
摘要： A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Status detection logic circuitry is included within the socket controller for detecting changes in status of selected signals and notifying the system adapter of the changes in status. This status detection logic circuitry ensures that multiple changes of status of the selected signals are recorded and reported to the system adapter in the order in which the changes occurred.
摘要翻译：被称为系统适配器和插座控制器的包括一对集成电路的外围接口系统和设备使用称为窗口 - 芯片间通信协议的通信协议来接口诸如PCMCIA卡或红外线设备和具有CPU系统总线的具有不同格式的其他子系统。系统适配器使用ATA通信标准与硬盘驱动器子系统进行通信，以将ATA硬盘驱动器与CPU系统总线进行接口。与PCMCIA外设卡和IR外围设备通信的系统适配器和插座控制器之间的通信使用可与其他通信协议共享硬件资源的窗口 - 芯片间通信协议实现。系统适配器和硬盘驱动器之间以及系统适配器和插座控制器之间的通信可以提供在标准40信号带状电缆的同一链上。状态检测逻辑电路包括在插座控制器内，用于检测所选信号状态的变化，并通知系统适配器的状态变化。该状态检测逻辑电路确保所选信号的状态的多次更改被记录并以发生更改的顺序报告给系统适配器。

4. 发明授权

US06633563B1 Assigning cell data to one of several processors provided in a data switch 有权
标题翻译：将单元数据分配给数据交换机中提供的多个处理器之一
公开(公告)号：US06633563B1
公开(公告)日：2003-10-14
申请号：US09260785
申请日：1999-03-02
申请人： Arthur Lin , Kent Huntley Headrick , Suhas Anand Shetty
发明人： Arthur Lin , Kent Huntley Headrick , Suhas Anand Shetty
IPC分类号： H04L1200
CPC分类号： H04L47/24 , H04L47/10 , H04L47/20
摘要： A content addressable memory (CAM) having a search field, a mask and an output for each CAM location is used to efficiently determine a processor for processing IP packets, with each IP packet being received as a sequence of cells. IP packets may be assigned to a processor (group) based on an examination of the header data, potentially including IP header and other higher layer protocols headers. The search field of a CAM location is pre-stored with header data, and the bit positions to be searched in the location are specified by using a mask. The output of the location identifies the processor group for executing packets with headers matching the search field, with only the bits specified by the mask being compared. When a first cell of an IP packet is received, the header data is provided as an input to the CAM, and the output identifies the processor (group) for executing the IP packet.
摘要翻译：使用具有每个CAM位置的搜索字段，掩码和输出的内容可寻址存储器（CAM）来有效地确定用于处理IP分组的处理器，其中每个IP分组被接收为单元格序列。可以基于头标数据的检查将IP分组分配给处理器（组），潜在地包括IP报头和其它更高层协议报头。使用头部数据预先存储CAM位置的搜索字段，并且使用掩码来指定要在该位置中搜索的比特位置。该位置的输出标识用于执行与搜索字段匹配的报头的处理器组，只有由掩码指定的位进行比较。当接收到IP分组的第一小区时，头部数据被提供给CAM的输入，并且输出标识用于执行IP分组的处理器（组）。

5. 发明授权

US06292492B1 Efficient method and apparatus for allocating memory space used for buffering cells received on several connections in an asynchronous transfer mode (ATM) switch 失效
标题翻译：用于分配用于缓冲在异步传输模式（ATM）交换机中的若干连接上接收的小区的存储空间的高效方法和装置
公开(公告)号：US06292492B1
公开(公告)日：2001-09-18
申请号：US09081969
申请日：1998-05-20
申请人： Flavio Giovanni Bonomi , Suhas Anand Shetty , De Bao Vu , William Stanley Evans
发明人： Flavio Giovanni Bonomi , Suhas Anand Shetty , De Bao Vu , William Stanley Evans
IPC分类号： H04L1254
CPC分类号： H04L12/5601
摘要： A switch guaranteeing a minimum amount of memory space for desired connection while allowing efficient dynamic change of maximum memory space that can be used by a connection. Only an amount of memory space which is required for guaranteeing the minimum amount of memory space is reserved. When the reserved space is decremented due to new cells being received on connections, the maximum memory space reserved for each connection is dynamically increased. For multicast connections, only a single copy of the cell data is stored even though a multicast cell is transmitted on several ports. Multicast cells can also be processed using the same signals used for processing unicast cells.
摘要翻译：一个交换机，保证最小量的内存空间用于所需的连接，同时允许有效的动态更改可由连接使用的最大内存空间。仅保留存储空间最小量所需的内存空间量。当由于在连接上接收到新单元而使保留空间减少时，为每个连接保留的最大存储空间被动态地增加。对于组播连接，即使多个小区在多个端口上传输，也只存储单元数据的一个副本。组播小区也可以使用用于处理单播小区的相同信号进行处理。

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