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1. 发明授权

US07080236B2 Updating stack pointer based on instruction bit indicator without executing an update microinstruction 失效
标题翻译：基于指令位指示器更新堆栈指针，而不执行更新微指令
公开(公告)号：US07080236B2
公开(公告)日：2006-07-18
申请号：US10262214
申请日：2002-09-30
申请人： Stephan J. Jourdan , Alan B. Kyker , Nicholas G. Samra
发明人： Stephan J. Jourdan , Alan B. Kyker , Nicholas G. Samra
IPC分类号： G06F9/312
CPC分类号： G06F9/38 , G06F9/30101
摘要： A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.
摘要翻译：一种堆栈指针更新技术，其中堆栈指针被更新而不执行微操作以添加或减去堆栈指针值。还描述了堆栈指针更新技术，以将堆栈指针重置为预定值，而不执行微操作以将堆栈指针值加或减。

2. 发明授权

US07321963B2 System and method for storing immediate data 失效
公开(公告)号：US07321963B2
公开(公告)日：2008-01-22
申请号：US10773848
申请日：2004-02-05
申请人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
发明人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
IPC分类号： G06F9/318 , G06F9/28
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/3016 , G06F9/30167
摘要： An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

3. 发明授权

US06493821B1 Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table 失效
标题翻译：使用指令序列号索引状态信息表从回写阶段事件信号或微分支错误预测中恢复
公开(公告)号：US06493821B1
公开(公告)日：2002-12-10
申请号：US09094027
申请日：1998-06-09
申请人： Reynold V. D'Sa , Robert F. Krick , Rebecca E. Hebda , Alan B. Kyker
发明人： Reynold V. D'Sa , Robert F. Krick , Rebecca E. Hebda , Alan B. Kyker
IPC分类号： G06F938
CPC分类号： G06F9/30174 , G06F9/3863
摘要： A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.
摘要翻译：提供流水线微处理器。流水线微处理器包括回写阶段，其向事件发信号并发送具有该事件的指令的序列号。事件可能是例如故障，陷阱或分支错误预测。流水线微处理器还包括解码级，其存储相应指令的恢复状态信息，并且响应于写回级，通过使用序列号来访问存储的信息以检索具有该事件的指令的恢复状态信息来发信号通知该事件。恢复状态信息可以包括例如指向下一个线性指令的指针，指向分支目标指令的指针，分支预测或指令源。事件恢复微码确定使用恢复状态信息执行的下一条指令，下一条指令在机器恢复后执行。

4. 发明授权

US10025343B2 Data transfer between asynchronous clock domains 有权
公开(公告)号：US10025343B2
公开(公告)日：2018-07-17
申请号：US13991602
申请日：2011-12-28
申请人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
发明人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
IPC分类号： G06F1/12 , G06F13/42
摘要： Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

5. 发明授权

US07730281B2 System and method for storing immediate data 失效
标题翻译：用于存储即时数据的系统和方法
公开(公告)号：US07730281B2
公开(公告)日：2010-06-01
申请号：US11974995
申请日：2007-10-17
申请人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
发明人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
IPC分类号： G06F9/318 , G06F9/28
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/3016 , G06F9/30167
摘要： An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.
摘要翻译：一种包含存储在存储介质上的指令的物品。该指令包括存储操作码信号的操作码字段和存储操作数信号的操作数字段。操作数在存储在操作数字段之前被压缩。

6. 发明授权

US06850961B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition 有权
标题翻译：基于检测失速条件在多线程处理器内执行线程切换操作的方法和系统
公开(公告)号：US06850961B2
公开(公告)日：2005-02-01
申请号：US10251583
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F9/38 , G06F9/48 , G06R9/60
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。检测与多线程处理器的处理器流水线内的第一线程有关的失速状态。也检测到在停止状态的检测之后的预定时间间隔的经过。响应于检测第一线程的第一预定量指令信息的调度和预定时间间隔的经过，对指令流缓冲器的输出进行线程切换操作。

7. 发明授权

US06795845B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction 有权
标题翻译：基于检测到分支指令，在多线程处理器内执行线程切换操作的方法和系统
公开(公告)号：US06795845B2
公开(公告)日：2004-09-21
申请号：US10251204
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。还检测从指令信息源发送的第一线程的指令信息内的分支指令。响应于分支指令的检测和对第一线程的第一预定量指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。因此开始从指令流缓存器发送第二线程的指令信息。

8. 发明授权

US06785890B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread 有权
标题翻译：在多线程处理器内执行线程切换操作的方法和系统，该方法和系统基于检测到一条线程的指令信息流不存在
公开(公告)号：US06785890B2
公开(公告)日：2004-08-31
申请号：US10251527
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F1500
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。检测到来自处理器管线中的上游源的第一线程的指令信息流不存在于指令信息源中。还检测到在检测到指令信息的流动之后的预定时间间隔的经过。响应于检测第一线程的第一预定量指令信息的调度，并且响应于预定时间间隔的经过，针对指令流缓冲器的输出执行线程切换操作。因此开始从指令流缓存器发送第二线程的指令信息。

9. 发明授权

US06308279B1 Method and apparatus for power mode transition in a multi-thread processor 失效
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06308279B1
公开(公告)日：2001-10-23
申请号：US09083281
申请日：1998-05-22
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F126
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

10. 发明授权

US07334115B1 Detection, recovery and prevention of bogus branches 失效
标题翻译：检测，恢复和预防假枝
公开(公告)号：US07334115B1
公开(公告)日：2008-02-19
申请号：US09608512
申请日：2000-06-30
申请人： Reynold V. D'Sa , Alan B. Kyker , Slade A. Morgan , Rebecca E. Hebda , Richard A. Weier , Robert F. Krick
发明人： Reynold V. D'Sa , Alan B. Kyker , Slade A. Morgan , Rebecca E. Hebda , Richard A. Weier , Robert F. Krick
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3808 , G06F9/3861
摘要： The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.
摘要翻译：本发明提供了一种用于检测和预防微处理器中的虚假分支预测和恢复的方法和装置。从宏指令解码的微操作被存储在解码的微操作高速缓存中。分支预测逻辑确定分支是否为假。如果所采取的分支被确定为假的，则本发明使得从原始虚假分支微操作指令下降的微操作被标记并随后移动到处理器的后端退休。此外，分支预测逻辑（分支预测逻辑存储缓冲器）被更新为分支的实际方向是什么。以这种方式，则检测到虚假的分支，从中进一步预防和恢复。

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