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1. 发明授权

US06308279B1 Method and apparatus for power mode transition in a multi-thread processor 失效
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06308279B1
公开(公告)日：2001-10-23
申请号：US09083281
申请日：1998-05-22
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F126
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

2. 发明授权

US06981163B2 Method and apparatus for power mode transition in a multi-thread processor 失效
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06981163B2
公开(公告)日：2005-12-27
申请号：US10887488
申请日：2004-07-07
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

3. 发明授权

US06775786B2 Method and apparatus for power mode transition in a multi-thread processor 有权
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06775786B2
公开(公告)日：2004-08-10
申请号：US09951908
申请日：2001-09-12
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F126
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

4. 发明授权

US09600285B2 Packed data operation mask concatenation processors, methods, systems and instructions 有权
公开(公告)号：US09600285B2
公开(公告)日：2017-03-21
申请号：US13977239
申请日：2011-12-22
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30 , G06F13/14
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F13/14
摘要： A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.

5. 发明授权

US09459866B2 Vector frequency compress instruction 有权
标题翻译：矢量频率压缩指令
公开(公告)号：US09459866B2
公开(公告)日：2016-10-04
申请号：US13993058
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
IPC分类号： G06F9/30 , H03M7/46 , H03M7/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/3016 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.
摘要翻译：一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中各自被压缩的相同数据元素的一个或多个游程作为值和游程长度对。目标操作数标识目标向量寄存器。处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定压缩值，后跟该运行的运行长度。

6. 发明申请

US20160179530A1 INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD 审中-公开
标题翻译：指令和逻辑执行矢量饱和的双重字/ QUADWORD ADD
公开(公告)号：US20160179530A1
公开(公告)日：2016-06-23
申请号：US14582007
申请日：2014-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal , Mark J. Charney , Milind B. Girkar
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal , Mark J. Charney , Milind B. Girkar
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F7/00 , G06F9/3001 , G06F9/30018
摘要： In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.
摘要翻译：在几个实施例中，指令集架构的向量扩展包括执行饱和有符号和无符号整数加法的指令。在一个实施例中，提供了带符号饱和的向量有符号整数加法。在一个实施例中，提供了具有无符号饱和度的向量无符号整数加法。在一个实施例中，带符号和无符号指令都支持打包的双字和四字整数。

7. 发明申请

US20150095614A1 APPARATUS AND METHOD FOR EFFICIENT MIGRATION OF ARCHITECTURAL STATE BETWEEN PROCESSOR CORES 审中-公开
标题翻译：处理器之间建筑状态有效迁移的装置和方法
公开(公告)号：US20150095614A1
公开(公告)日：2015-04-02
申请号：US14040230
申请日：2013-09-27
申请人： Bret L. Toll , Scott D. Hahn , Jason W. Brandt , Thomas F. Toll
发明人： Bret L. Toll , Scott D. Hahn , Jason W. Brandt , Thomas F. Toll
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3851 , G06F9/4856
摘要： An apparatus and method are described for the efficient migration of architectural state between processor cores. For example, a processor according to one embodiment comprises: a first processing core having a first instruction execution pipeline including first register set for storing a first architectural state of a first thread being executed thereon; a second processing core having a second instruction execution pipeline including a second register set for storing a second architectural state of a second thread being executed thereon; and architectural state migration logic to perform a direct, simultaneous swap of the first architectural state from the first register set with the second architectural state from the second register set responsive to detecting that the execution of the first thread is to be migrated from the first core to the second core.
摘要翻译：描述了用于处理器核心之间架构状态的有效迁移的装置和方法。例如，根据一个实施例的处理器包括：具有第一指令执行流水线的第一处理核心，第一指令执行流水线包括用于存储在其上执行的第一线程的第一架构状态的第一寄存器集; 第二处理核心，具有第二指令执行流水线，该第二指令执行流水线包括第二寄存器组，用于存储在其上执行的第二线程的第二架构状态; 以及体系结构状态迁移逻辑，用于响应于检测到要从第一核心迁移第一线程的执行，执行来自第二架构状态的第一寄存器与第二寄存器集的第一架构状态的直接同时交换到第二个核心。

8. 发明申请

US20140379996A1 METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：方法，装置和系统的交互式分析控制指令
公开(公告)号：US20140379996A1
公开(公告)日：2014-12-25
申请号：US13997245
申请日：2012-02-02
申请人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Robert S. Chappell , Bret L. Toll
发明人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Robert S. Chappell , Bret L. Toll
IPC分类号： G06F9/52 , G06F12/08 , G06F9/46
摘要： An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.
摘要翻译：这里描述了一种用于提供推测逃逸指令的装置和方法。具体地，本文描述了显式的非事务性加载操作。在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。然而，程序员或编译器可以利用显式的非事务性读取从存储器地址加载到目标寄存器中，而不将读取/加载添加到事务读取集合。同样，也提供非事务存储。这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。

9. 发明申请

US20140281457A1 METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权
标题翻译：用于打造异质系统并提供对称核心视图的方法
公开(公告)号：US20140281457A1
公开(公告)日：2014-09-18
申请号：US13854001
申请日：2013-03-29
申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
摘要翻译：描述异构处理器架构和启动异构处理器的方法。根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

10. 发明申请

US20140281401A1 Systems, Apparatuses, and Methods for Determining a Trailing Least Significant Masking Bit of a Writemask Register 有权
标题翻译：用于确定写掩码寄存器的尾随最低有效屏蔽位的系统，设备和方法
公开(公告)号：US20140281401A1
公开(公告)日：2014-09-18
申请号：US13840809
申请日：2013-03-15
申请人： Christopher J. Hughes , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Elmoustapha Ould-Ahmed_Vall , Bret L. Toll , Robert Valentine
发明人： Christopher J. Hughes , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Elmoustapha Ould-Ahmed_Vall , Bret L. Toll , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/30018 , G06F9/30036
摘要： The execution of a KZBTZ finds a trailing least significant zero bit position in an first input mask and sets an output mask to have the values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in an first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask.
摘要翻译： KZBTZ的执行在第一输入掩码中找到尾随的最低有效零位位置，并将输出掩码设置为具有第一输入掩码的值，但是所有位位置都比接近最低有效位更靠近最高有效位位置第一个输入掩码中的零位位置设置为零。在一些实施例中，使用第二输入掩码作为写掩码，使得根据第二输入掩码中的相应位位置，在尾随最低有效零位位置计算中不考虑第一输入掩码的位位置。

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