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1. 发明授权

US06246289B1 Variable-gain multistage amplifier with broad bandwidth and reduced phase variations 有权
标题翻译：可变增益多级放大器，带宽宽，相位变化减小
公开(公告)号：US06246289B1
公开(公告)日：2001-06-12
申请号：US09507562
申请日：2000-02-18
申请人： Valerio Pisati , Salvatore Portaluri , Alessandro Savo , Stefano Marchese
发明人： Valerio Pisati , Salvatore Portaluri , Alessandro Savo , Stefano Marchese
IPC分类号： H03F345
CPC分类号： H03G1/0023
摘要： A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors. The amplifier further includes two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.
摘要翻译：一种具有宽带宽和相位变化较小的可编程增益多级放大器，具有由第一电流源偏置的差分输入级，馈送差分电压信号，该级连接到阴极端子连接的一对二极管到由双极晶体管的集电极端子提供的由第二电流源偏置并且其中集电极端子连接到负载电阻器的各个双极晶体管，放大器的差分输出被提供。放大器还包括两个电路分支，每个电路分支由双极晶体管和第三电流源构成，第三电流源分别连接到双极晶体管的集电极端子和发射极端子，其中基极端子接收差分电压信号并且集电极端子连接到两个二极管中的相应一个的阴极端子，电路分支通过一对电容器相互连接。

2. 发明授权

US6037838A Amplifier with programmable gain and input linearity usable in high-frequency lines 有权
标题翻译：具有可编程增益和输入线性度的放大器可用于高频线路
公开(公告)号：US6037838A
公开(公告)日：2000-03-14
申请号：US264296
申请日：1999-03-08
申请人： Stefano Marchese , Valerio Pisati , Salvatore Portaluri , Alessandro Savo
发明人： Stefano Marchese , Valerio Pisati , Salvatore Portaluri , Alessandro Savo
IPC分类号： H03G1/00 , H03G7/06 , H03F3/45 , H03G7/00
CPC分类号： H03G7/06 , H03G1/0023
摘要： An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.
摘要翻译：在高频下具有可编程增益和输入线性度的放大器可以增加增益，而不会影响输入线性度并且不会显着增加电流消耗。放大器包括输入级，其接收用于通过压缩执行其电流转换的电压信号。输出级连接到输入级，并且解压缩由输入级提供的信号，以产生其增益放大。放大器还包括插入在输入级和输出级之间的至少一个电流放大器级。至少一个电流放大器包括串联连接到负载二极管和电流源的至少一个双极晶体管。在所述至少一个放大器级中提供所述负载二极管的跨导的减小以确定所述放大器的可编程增益因子。

3. 发明授权

US06424172B1 Circuit structure for synthesizing time-continual filters 有权
标题翻译：用于合成时间连续滤波器的电路结构
公开(公告)号：US06424172B1
公开(公告)日：2002-07-23
申请号：US09796996
申请日：2001-02-28
申请人： Valerio Pisati , Salvatore Portaluri , Marco Cazzaniga , Rinaldo Castello
发明人： Valerio Pisati , Salvatore Portaluri , Marco Cazzaniga , Rinaldo Castello
IPC分类号： H03K19082
CPC分类号： H03H11/0422
摘要： This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor. Thus, a released “zero” can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
摘要翻译：本发明涉及具有可编程零点的前馈类型的电路结构，特别是用于合成时间连续滤波器。该结构包括互连至少一个互连节点并连接在第一单元的第一信号输入和第二单元的输出端之间的一对放大单元，每个单元包括一对具有共同的导通端子并具有其它导电端子通过相应的偏置构件分别耦合到第一电压基准。所述结构还包括将所述第一单元的节点连接到所述输出端子并且包括具有连接到所述第一单元的节点的控制端子的晶体管，连接到所述输出端子的第一导通端子和第二导通端子通过电容器耦合到第二参考电压。因此，可以在极零复平面的右半平面中引入释放的“零”，以改善组增益的平坦化。

4. 发明授权

US6133771A Device for generating pulses of high-precision programmable duration 有权
标题翻译：用于产生高精度可编程持续时间的脉冲的装置
公开(公告)号：US6133771A
公开(公告)日：2000-10-17
申请号：US263757
申请日：1999-03-05
申请人： Salvatore Portaluri , Valerio Pisati , Luigi Zangrandi
发明人： Salvatore Portaluri , Valerio Pisati , Luigi Zangrandi
IPC分类号： H03K7/08 , H03K3/17
CPC分类号： H03K7/08
摘要： A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.
摘要翻译：器件产生具有可编程持续时间的高精度脉冲。该装置包括第一，第二和第三脉冲发生器电路。第一脉冲发生器电路在输入端接收脉冲产生指令信号，并在输出端提供用于将寄存器的内容装入计数器的第一脉冲。第二脉冲发生器电路由第一脉冲发生器电路提供的第一脉冲触发。第三脉冲发生器电路由第二脉冲发生器电路提供的第二脉冲触发，并产生第三脉冲以重新启动第二脉冲发生器电路。由第二脉冲发生器电路提供的第二脉冲为计数器形成时钟信号以产生计数器的减量。来自计数器的输出信号是要产生的脉冲信号。脉冲信号的持续时间由计数器的内容决定。

5. 发明授权

US6127873A Feedforward circuit structure with programmable zeros for providing programmable group delay of a wide signal band 有权
标题翻译：具有可编程零点的前馈电路结构，用于提供宽信号频带的可编程组延迟
公开(公告)号：US6127873A
公开(公告)日：2000-10-03
申请号：US221199
申请日：1998-12-23
申请人： Salvatore Portaluri , Valerio Pisati
发明人： Salvatore Portaluri , Valerio Pisati
IPC分类号： G05B19/00 , H03H11/04 , H03H11/26
CPC分类号： H03H11/04
摘要： A feedforward circuit structure with programmable zeros for synthesizing continuous-time filters, delay lines, and the like is described. The circuit comprises a first cell and a second cell which are cascade-connected. Each one of the first and second cells comprises first and second pairs of bipolar transistors. The emitter terminals of the first pair of transistors are connected to a first current source, and the emitter terminals of the second pair of transistors are connected to a second current source. A first high-impedance element is connected between the first and second pairs of transistors, and a second high-impedance element is connected at an output of the second pair of transistors. A fifth transistor is connected between the collector terminal of a first transistor of the first pair of transistors and the collector terminal of a second transistor of the second pair of transistors. The base terminal of the fifth transistor receives a signal which is taken from the collector terminal of the first transistor of the first pair of transistors, with the signal being taken with a positive sign in the first cell and with a negative sign in the second cell, in order to determine a transfer function with a pair of singularities at the numerator. The second transistors of the first and second pairs of transistors are controlled respectively by third and fourth current sources which have mutually different values.
摘要翻译：描述了具有用于合成连续时间滤波器，延迟线等的可编程零的前馈电路结构。电路包括级联的第一单元和第二单元。第一和第二单元中的每一个包括第一和第二对双极晶体管。第一对晶体管的发射极端子连接到第一电流源，第二对晶体管的发射极端子连接到第二电流源。第一高阻抗元件连接在第一和第二对晶体管之间，第二高阻抗元件连接在第二对晶体管的输出端。第五晶体管连接在第一对晶体管的第一晶体管的集电极端子与第二对晶体管的第二晶体管的集电极端子之间。第五晶体管的基极接收从第一晶体管的第一晶体管的集电极端子取出的信号，信号以第一单元中的正号取，第二单元中具有负号，以便在分子处确定具有一对奇异点的传递函数。第一和第二对晶体管的第二晶体管分别由具有相互不同的值的第三和第四电流源控制。

6. 发明授权

US06359503B1 Basic cell for programmable analog time-continuous filter 失效
标题翻译：可编程模拟时间连续滤波器的基本单元
公开(公告)号：US06359503B1
公开(公告)日：2002-03-19
申请号：US08999962
申请日：1997-08-12
申请人： Roberto Alini , Francesco Brianti , Valerio Pisati , Marco Demicheli
发明人： Roberto Alini , Francesco Brianti , Valerio Pisati , Marco Demicheli
IPC分类号： H03K500
CPC分类号： H03H15/00 , H02P6/21 , H03H11/0422
摘要： An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node. “Elementary cell structure for programmable time-continuous analog filters and in particular for read/write operations on magnetic supports and associated analog filter”
摘要翻译：用于可编程时间连续模拟滤波器的基本单元结构，特别是用于在磁性支撑上的读取/写入操作中处理模拟信号的基本单元结构包括：放大器级，其设置有一对在公共电路节点中连接在一起的结构相同的跨导半电池。这种类型的单元级联提供了一种时间连续的模拟延迟线，其用于横向时间连续的模拟滤波器。该滤波器包括通过乘法器节点连接到最终求和节点的相同延迟线级联。 “用于可编程时间连续模拟滤波器的基本单元结构，特别是用于磁性支持和相关模拟滤波器的读/写操作”

7. 发明授权

US5621358A Transconductor stage with controlled gain 失效
标题翻译：具有受控增益的跨导级
公开(公告)号：US5621358A
公开(公告)日：1997-04-15
申请号：US454924
申请日：1995-05-31
申请人： Valerio Pisati , Roberto Alini , Rinaldo Castello , Gianfranco Vai
发明人： Valerio Pisati , Roberto Alini , Rinaldo Castello , Gianfranco Vai
IPC分类号： H03F3/343 , H03F3/45 , H03G1/00 , H03H11/24
CPC分类号： H03F3/45883 , H03F3/45286 , H03F3/45807 , H03G1/0023 , H03F2203/45648
摘要： A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.
摘要翻译：包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3）的受控增益跨导体（20），连接到跨导级和连接在所述输出端子（O1，O2）和有源负载（4）之间的有源负载（4）的控制电路（5）。还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出，以提供调整装置的DC增益所需的预定电压值（Vc）。

8. 发明授权

US07061300B2 Low supply voltage analog multiplier 失效
标题翻译：低电源模拟乘法器
公开(公告)号：US07061300B2
公开(公告)日：2006-06-13
申请号：US09797204
申请日：2001-02-27
申请人： Valerio Pisati , Marco Cazzaniga , Alessandro Venca
发明人： Valerio Pisati , Marco Cazzaniga , Alessandro Venca
IPC分类号： G05F1/10
CPC分类号： G06G7/163 , H03D7/1408 , H03D7/1433 , H03D7/1491 , H03D2200/0086
摘要： The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
摘要翻译：本发明涉及一种低电源模拟乘法器，其包括一对差分单元，每个单元包括一对具有耦合发射极的双极晶体管。每个单元的第一晶体管在其基极端子上接收输入信号，并且其集电极端子通过偏置构件耦合到第一电压基准。有利地，每个单元的第二晶体管是二极管配置，并且这些单元在对应于每对中的第二晶体管的基极端子的公共节点处互连。该乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及降低的输出信号的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。

9. 发明授权

US5821829A Integrated circuit waith automatic compensation for deviations of the capacitances from nominal values 失效
标题翻译：集成电路，具有自动补偿电容与标称值的偏差
公开(公告)号：US5821829A
公开(公告)日：1998-10-13
申请号：US810032
申请日：1997-03-04
申请人： Melchiorre Bruccoleri , Gaetano Cosentino , Marco Demicheli , Valerio Pisati
发明人： Melchiorre Bruccoleri , Gaetano Cosentino , Marco Demicheli , Valerio Pisati
IPC分类号： H03L7/099 , H03K3/281 , H03L7/00
CPC分类号： H03L7/0805 , H03L7/099
摘要： The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.
摘要翻译：该系统包括各自具有电容器的电路单元和用于根据充电电流和电容器的电容之间的比率（I / C）定义量的充电电路。为了自动补偿由于集成电路制造过程的参数波动引起的实际电容与标称电容的偏差，系统具有使用电路单元之一作为可调谐振荡器的锁相环，以及电流传感器装置，其根据振荡器的电容器的调节的充电电流或PLL环路的误差电流来调节电路单元的电容器的充电电流。

10. 发明授权

US6078462A Device and method for processing servo signals in a parallel architecture PRML reading apparatus for hard disks 失效
标题翻译：用于硬盘并行架构PRML读取装置处理伺服信号的装置和方法
公开(公告)号：US6078462A
公开(公告)日：2000-06-20
申请号：US996915
申请日：1997-12-23
申请人： Maurizio Zuffada , Paolo Gadducci , David Moloney , Valerio Pisati
发明人： Maurizio Zuffada , Paolo Gadducci , David Moloney , Valerio Pisati
IPC分类号： G11B20/14 , G11B5/02 , G11B5/09 , G11B5/596 , G11B20/06 , G11B20/10 , G11B20/18 , G11B21/10
CPC分类号： G11B20/10009 , G11B21/106
摘要： The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.
摘要翻译：该装置将与包括可变增益输入放大器，低通模拟滤波器，横向连续时间模拟滤波器和两个截然不同并行的处理通道之间的并行架构部分响应最大似然（PRML）读取装置一起使用横向模拟滤波器和RLL-NRZ解码器。两个处理通道包括相应的模拟 - 数字转换器和相应的维特比检测器，并且根据彼此交替的采样序列进行操作。用于处理伺服信号的装置包括连接到模数转换器和积分器的输出的整流器。

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