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    • 3. 发明授权
    • Low offset push-pull amplifier
    • 低偏移推挽放大器
    • US5963065A
    • 1999-10-05
    • US787301
    • 1997-01-24
    • Roberto AliniMelchiorre BruccoleriGaetano CosentinoValerio Pisati
    • Roberto AliniMelchiorre BruccoleriGaetano CosentinoValerio Pisati
    • H03F3/30H03F3/34H03F3/26
    • H03F3/3077
    • A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).
    • 低失调放大器具有由推挽装置中的npn晶体管和pnp晶体管构成的输出级和驱动级。 后者包括电流镜电路,其在其输入支路中具有与第一恒定电流发生器串联的pnp晶体管,并且在其输出支路中具有npn晶体管,以及两个互补双极晶体管,其中集电极连接到输出端 端子和基极连接到放大器的输入端子。 驱动器级的pnp晶体管的发射极通过第二恒流发生器连接到电源的正极端子,并连接到输出级的npn晶体管的基极,驱动器级的npn晶体管的发射极 通过电流镜电路的输出支路的npn晶体管和输出级的pnp晶体管的基极连接到电源的负极。 放大器具有非常低或零偏移(Vos = Vout-Vin)。
    • 7. 发明授权
    • Differential charge pump using surtchingly controlled current generators
    • 差动电荷泵采用交流电流发生器
    • US5736880A
    • 1998-04-07
    • US576882
    • 1995-12-21
    • Melchiorre BruccoleriGaetano CosentinoMarco DemicheliGiuseppe Patti
    • Melchiorre BruccoleriGaetano CosentinoMarco DemicheliGiuseppe Patti
    • H03L7/093H03L7/089H03L7/06
    • H03L7/0896
    • A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by switchingly controlled current generators. The differential charge pump employs two identical current generators for injecting the same current I in a substantially continuous manner, on the two significant nodes of the lowpass filter. The differential charge pump also employs two pairs of identical, switchingly controlled current generators connected to the two significant nodes, respectively, each capable of pulling a current I. The two generators forming each of the two pairs of switchingly controlled current generators are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of the pair of control signals, respectively. All four switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision. The two identical (P-type) current generators employed for continuously injecting the same current I on the two nodes of the lowpass filter may be controlled through a common mode feedback loop for enhanced precision.
    • 采用低通滤波器网络的差分电荷泵电路,该低通滤波器网络可由切换控制的电流发生器进行充电和放电。 差分电荷泵采用两个相同的电流发生器,以基本上连续的方式在低通滤波器的两个重要节点上注入相同的电流I。 差分电荷泵还采用两对相同的交换控制电流发生器,分别连接到两个有效节点,每个有效节点能够拉电流I.形成两对开关控制电流发生器中的每一对的两个发电机由一个 一对控制信号(UP,DOWN)和另一对控制信号的反相信号。 所有四个交流控制发电机可以是相同类型(N型),从而确保高速度和精度。 用于在低通滤波器的两个节点上连续注入相同电流I的两个相同(P型)电流发生器可以通过共模反馈回路来控制,以提高精度。
    • 9. 发明授权
    • BiCMOS transconductor stage for high-frequency filters
    • BiCMOS跨导级高频滤波器
    • US5912582A
    • 1999-06-15
    • US866889
    • 1997-05-30
    • Valerio PisatiRoberto AliniGaetano CosentinoGianfranco Vai
    • Valerio PisatiRoberto AliniGaetano CosentinoGianfranco Vai
    • H03F3/45H03F3/72H03B1/00H03K5/00H04B1/10
    • H03F3/72H03F3/45286H03F2203/45302H03F2203/45304H03F2203/45371H03F2203/45396H03F2203/45506
    • A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor. In a variant differential stage, there are also provided respective added MOS transistors connected in parallel with the MOS transistors of the input circuit portion to change the ratio W:L of each of the MOS transistors.
    • 用于高频滤波器的BiCMOS跨导差分级包括具有信号输入的输入电路部分和具有对应于信号输入的各自的栅极端子的一对MOS晶体管。 差分级具有具有信号输出的输出电路部分和一对双极晶体管,它们以共模基极连接在共模基底上,该公共基极以共源共栅配置插入在输入端和输出端之间。 差分级包括与双极晶体管中的至少一个相关联的开关器件,以改变差分级中存在的寄生电容器之间的连接。 开关器件还具有至少一个加法双极晶体管,其以可移除的方式与相应的双极共源共栅晶体管并联连接。 在变异差分级中,还提供了与输入电路部分的MOS晶体管并联连接的各个附加的MOS晶体管,以改变每个MOS晶体管的比率W:L。
    • 10. 发明授权
    • Method for reducing the settling time in PLL circuits
    • 降低PLL电路稳定时间的方法
    • US06636576B1
    • 2003-10-21
    • US09413713
    • 1999-10-05
    • Pietro FiloramoGaetano Cosentino
    • Pietro FiloramoGaetano Cosentino
    • H03L7093
    • H03L7/189
    • A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (VC) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (VC) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (IDAC) of the digital-analog converter such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter keeps the filter voltage (Vf) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.
    • 一种用于减少PLL电路中的建立时间的方法,特别是用于RF收发器中的PLL电路包括相位比较器,滤波器,数模转换器和加法器,其适于在输出端产生电压(VC) 用于控制通过变容二极管提供的压控振荡器,所述方法包括确定压控振荡器的控制电压(VC)对发射机所选频道的频率的依赖性; 以及产生描述所述数模转换器的输出电流(IDAC)的变化的定律,使得从所述数模转换器的输出电流获得的电压(VDAC)加到所述滤波器的输出电压(Vf)上 保持滤波电压(Vf)恒定,以便随着所选通道的变化而减小PLL电路的稳定时间。