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1. 发明申请

US20090031733A1 THERMOTUNNELING REFRIGERATION SYSTEM 审中-公开
标题翻译：热交换制冷系统
公开(公告)号：US20090031733A1
公开(公告)日：2009-02-05
申请号：US11830890
申请日：2007-07-31
申请人： Stanton Earl Weaver, JR. , Mehmet Arik , James William Bray , Ahmed Elasser , Robert John Wojnarowski , Mark Wayne Wilson , Jason Knud Klindtworth , Surajit Atha
发明人： Stanton Earl Weaver, JR. , Mehmet Arik , James William Bray , Ahmed Elasser , Robert John Wojnarowski , Mark Wayne Wilson , Jason Knud Klindtworth , Surajit Atha
IPC分类号： F25B21/02
CPC分类号： F25B21/00 , F25B2321/003 , Y02B30/66
摘要： A refrigeration system is provided. The refrigeration system includes at least one thermal blocking thermotunneling device. The thermal blocking thermotunneling device comprises a first and a second surface separated by a nanoscale gap of less than about 20 nm, such that tunneling of electrons causes a unidirectional transfer of heat from the first surface to the second surface. Further, the at least one thermal blocking thermotunneling device has a thermal back path of less than about 70 percent.
摘要翻译：提供制冷系统。制冷系统包括至少一个热阻热电火花钻孔装置。热阻焊热电火焰装置包括由小于约20nm的纳米尺度间隙分开的第一和第二表面，使得电子的隧穿导致热量从第一表面到第二表面的单向转移。此外，所述至少一个热阻焊热电火花钻孔装置具有小于约70％的热回路径。

2. 发明申请

US20080305582A1 POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE 有权
标题翻译：功率半导体封装方法与结构
公开(公告)号：US20080305582A1
公开(公告)日：2008-12-11
申请号：US11846024
申请日：2007-08-28
申请人： Raymond Albert Fillion , Richard Alfred Beaupre , Ahmed Elasser , Robert John Wojnarowski , Charles Steven Korman
发明人： Raymond Albert Fillion , Richard Alfred Beaupre , Ahmed Elasser , Robert John Wojnarowski , Charles Steven Korman
IPC分类号： H01L21/50
CPC分类号： H01L23/4821 , H01L23/4822 , H01L23/5385 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/83 , H01L25/072 , H01L2224/2402 , H01L2224/24226 , H01L2224/2518 , H01L2224/32225 , H01L2224/72 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/83801 , H01L2224/92144 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.
摘要翻译：通过使用具有两个表面的电介质膜和具有接触焊盘的有源表面的功率半导体芯片来制造半导体芯片封装结构。使用粘合剂层来连接电介质膜的第一表面和功率半导体芯片的有源表面。形成邻近膜的第二表面的图案化导电层，延伸穿过膜中的孔到接触垫。

3. 发明授权

US07829386B2 Power semiconductor packaging method and structure 有权
标题翻译：功率半导体封装方法和结构
公开(公告)号：US07829386B2
公开(公告)日：2010-11-09
申请号：US11846024
申请日：2007-08-28
申请人： Raymond Albert Fillion , Richard Alfred Beaupre , Ahmed Elasser , Robert John Wojnarowski , Charles Steven Korman
发明人： Raymond Albert Fillion , Richard Alfred Beaupre , Ahmed Elasser , Robert John Wojnarowski , Charles Steven Korman
IPC分类号： H01L21/48 , H01L23/34
CPC分类号： H01L23/4821 , H01L23/4822 , H01L23/5385 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/83 , H01L25/072 , H01L2224/2402 , H01L2224/24226 , H01L2224/2518 , H01L2224/32225 , H01L2224/72 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/83801 , H01L2224/92144 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.
摘要翻译：通过使用具有两个表面的电介质膜和具有接触焊盘的有源表面的功率半导体芯片来制造半导体芯片封装结构。使用粘合剂层来连接电介质膜的第一表面和功率半导体芯片的有源表面。形成邻近膜的第二表面的图案化导电层，延伸穿过膜中的孔到接触垫。

4. 发明授权

US07262444B2 Power semiconductor packaging method and structure 有权
标题翻译：功率半导体封装方法和结构
公开(公告)号：US07262444B2
公开(公告)日：2007-08-28
申请号：US11205903
申请日：2005-08-17
申请人： Raymond Albert Fillion , Richard Alfred Beaupre , Ahmed Elasser , Robert John Wojnarowski , Charles Steven Korman
发明人： Raymond Albert Fillion , Richard Alfred Beaupre , Ahmed Elasser , Robert John Wojnarowski , Charles Steven Korman
IPC分类号： H01L31/111 , H01L21/48
CPC分类号： H01L23/4822 , H01L23/4821 , H01L23/5385 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/072 , H01L2224/2402 , H01L2224/24137 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/92135 , H01L2224/92144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.
摘要翻译：一种半导体芯片封装结构，包括具有与至少一个功率半导体芯片的一个或多个接触焊盘对准的一个或多个通孔的电介质膜。与电介质膜相邻的图案化导电层具有一个或多个导电柱，其延伸穿过与接触焊盘对准的一个或多个通孔，以将导电层电耦合到接触焊盘。在某些实施例中，可以在介电膜和至少一个功率半导体芯片的有源表面之间形成一个或多个气隙。还公开了制造半导体芯片封装结构的方法。

5. 发明申请

US20140005845A1 SYSTEM AND METHOD FOR DESIGN AND OPTIMIZATION OF GRID CONNECTED PHOTOVOLTAIC POWER PLANT WITH MULTIPLE PHOTOVOLTAIC MODULE TECHNOLOGIES 有权
标题翻译：用多光伏模块技术设计和优化网格连接光伏电站的系统和方法
公开(公告)号：US20140005845A1
公开(公告)日：2014-01-02
申请号：US13535617
申请日：2012-06-28
申请人： Bex George Thomas , Ahmed Elasser , Srinivas Bollapragada , Anthony William Galbraith , Mohammed Agamy , Maxim Valeryevich Garifullin
发明人： Bex George Thomas , Ahmed Elasser , Srinivas Bollapragada , Anthony William Galbraith , Mohammed Agamy , Maxim Valeryevich Garifullin
IPC分类号： G05F5/00
CPC分类号： H02J3/385 , Y02E10/58
摘要： A system and method of using one or more DC-DC/DC-AC converters and/or alternative devices allows strings of multiple module technologies to coexist within the same PV power plant. A computing (optimization) framework estimates the percentage allocation of PV power plant capacity to selected PV module technologies. The framework and its supporting components considers irradiation, temperature, spectral profiles, cost and other practical constraints to achieve the lowest levelized cost of electricity, maximum output and minimum system cost. The system and method can function using any device enabling distributed maximum power point tracking at the module, string or combiner level.
摘要翻译：使用一个或多个DC-DC / DC-AC转换器和/或替代设备的系统和方法允许多个模块技术的串串在同一个光伏发电厂内共存。计算（优化）框架估计了所选PV模块技术的光伏发电厂容量的百分比分配。框架及其配套组件考虑了辐射，温度，光谱曲线，成本和其他实际限制，以实现电力成本最低化，最大输出和最低系统成本。该系统和方法可以使用任何设备在模块，串或组合器级上实现分布式最大功率点跟踪。

6. 发明申请

US20060068611A1 Heat transfer device and system and method incorporating same 审中-公开
标题翻译：传热装置及其结合的系统和方法
公开(公告)号：US20060068611A1
公开(公告)日：2006-03-30
申请号：US10955639
申请日：2004-09-30
申请人： Stanton Weaver , James Bray , Ahmed Elasser , Seth Taylor
发明人： Stanton Weaver , James Bray , Ahmed Elasser , Seth Taylor
IPC分类号： H05K1/00 , C23C14/00 , B32B37/00 , H01S4/00
CPC分类号： H01J45/00 , B32B2310/024 , H01L35/00 , Y10T29/49002
摘要： A method of manufacturing a heat transfer device including providing first and second thermally conductive substrates that are substantially atomically flat, providing a patterned electrical barrier on the first or second thermally conductive substrates and disposing a low work function material on the first or second thermally conductive substrates in an area oriented between the patterned electrical barrier in a configuration in which the first and second thermally conductive substrates are positioned opposite from one another. The method also includes bonding the first and second thermally conductive substrates in the configuration and extracting a plurality of units having opposite sections of the first and second thermally conductive substrates, each unit having a portion of the patterned electrical barrier disposed about the low work function material.
摘要翻译：一种制造传热装置的方法，包括提供基本上原子上平坦的第一和第二导热基板，在第一或第二导热基板上提供图案化的电阻挡层，并将低功函数材料设置在第一或第二导热基板上在其中第一和第二导热基板彼此相对定位的构造中的图案化电阻挡之间的区域中。该方法还包括将第一导热基板和第二导热基板结合在一起并且提取具有第一和第二导热基板的相对部分的多个单元，每个单元具有围绕低功函数材料设置的图案化电阻挡部分。

7. 发明授权

US06629044B1 Electrical distribution analysis method and apparatus 有权
标题翻译：配电分析方法及装置
公开(公告)号：US06629044B1
公开(公告)日：2003-09-30
申请号：US09528140
申请日：2000-03-17
申请人： Thomas F. Papallo, Jr. , Sriram Ramakrishnan , Ahmed Elasser
发明人： Thomas F. Papallo, Jr. , Sriram Ramakrishnan , Ahmed Elasser
IPC分类号： G06F1900
CPC分类号： H02H6/00 , G06F17/5036 , H01H1/2058 , H01H11/0062
摘要： An apparatus and method for analyzing an apparatus, typically an electrical distribution system is provided. The apparatus and method is particularly useful for analyzing selective electrical distribution systems. The apparatus is generally a software system including a solver system for generating an output from an input presented to the solver system. The input is a mathematical representation of at least a portion of the electrical distribution system. In one embodiment, the input is presented to a model within the solver system. The model represents at least a portion of the electrical distribution system. The software system is capable of interfacing output data from one or more models with additional models for analyzing generally how devices within an electrical distribution system behave under certain conditions.
摘要翻译：提供一种用于分析装置（通常为配电系统）的装置和方法。该装置和方法对于分析选择性配电系统特别有用。该装置通常是包括用于从提供给求解器系统的输入产生输出的求解器系统的软件系统。输入是配电系统的至少一部分的数学表示。在一个实施例中，将输入呈现给解算器系统内的模型。该模型代表配电系统的至少一部分。软件系统能够将来自一个或多个模型的输出数据与附加模型进行接口，以便一般地分析配电系统中的设备在某些条件下的行为。

8. 发明授权

US06253115B1 System for implementing a design for six sigma process 失效
标题翻译：实施六西格玛工艺设计的系统
公开(公告)号：US06253115B1
公开(公告)日：2001-06-26
申请号：US09218685
申请日：1998-12-22
申请人： Arlie Russell Martin , Ahmed Elasser , Mohamed Ahmed Ali , Virendra Kumar , Jan Henning Aase , Brian Eric Lindholm , Mark Andrew Kolb
发明人： Arlie Russell Martin , Ahmed Elasser , Mohamed Ahmed Ali , Virendra Kumar , Jan Henning Aase , Brian Eric Lindholm , Mark Andrew Kolb
IPC分类号： G06F1900
CPC分类号： G06F17/50
摘要： A system for implementing a design for six sigma process having a plurality of sub-processes each having a plurality of sub-steps. The system includes an independent main application for implementing the design for six sigma process. A series of independent sub-process applications each implements one sub-process of the design for six sigma process. A tool library containing a plurality of executable tools is accessible by the main application and sub-process applications to access and execute the plurality of executable tools. A communications path interconnects the main application, the sub-process applications, and the tool library.
摘要翻译：一种用于实现具有多个子处理的具有多个子步骤的六西格玛处理设计的系统。该系统包括一个独立的主要应用程序，用于实现六西格玛过程的设计。一系列独立的子过程应用程序每个都实现了一个六步法设计的一个子过程。包含多个可执行工具的工具库可由主应用程序和子过程应用程序访问以访问和执行多个可执行工具。通信路径将主应用程序，子进程应用程序和工具库互连。

9. 发明授权

US09633998B2 Semiconductor device and method for making the same 有权
公开(公告)号：US09633998B2
公开(公告)日：2017-04-25
申请号：US13613848
申请日：2012-09-13
申请人： Stanislav Ivanovich Soloviev , Ahmed Elasser , Alexander Viktorovich Bolotnikov , Alexey Vert , Peter Almern Losee
发明人： Stanislav Ivanovich Soloviev , Ahmed Elasser , Alexander Viktorovich Bolotnikov , Alexey Vert , Peter Almern Losee
IPC分类号： H01L29/15 , H01L27/06 , H01L27/08
CPC分类号： H01L27/0676 , H01L27/0817 , H01L27/1443 , H01L27/14609 , H01L29/66363 , H01L29/7412
摘要： A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.

10. 发明授权

US09006027B2 Systems and methods for terminating junctions in wide bandgap semiconductor devices 有权
标题翻译：用于在宽带隙半导体器件中终止结的系统和方法
公开(公告)号：US09006027B2
公开(公告)日：2015-04-14
申请号：US13610614
申请日：2012-09-11
申请人： Zachary Matthew Stum , Ahmed Elasser , Stephen Daley Arthur , Stanislav I. Soloviev , Peter Almern Losee
发明人： Zachary Matthew Stum , Ahmed Elasser , Stephen Daley Arthur , Stanislav I. Soloviev , Peter Almern Losee
IPC分类号： H01L21/00 , H01L31/0328 , H01L29/06 , H01L29/74 , H01L29/87 , H01L21/02 , H01L29/73 , H01L29/739 , H01L29/16 , H01L29/20
CPC分类号： H01L29/0661 , H01L21/02107 , H01L29/063 , H01L29/1608 , H01L29/2003 , H01L29/73 , H01L29/7395 , H01L29/74 , H01L29/87
摘要： An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.
摘要翻译：电气装置包括设置在基底层顶部的阻挡层，其中阻挡层和基底层各自是宽带隙半导体，并且阻挡层和基底层在电气装置中形成掩埋结。该装置包括设置在阻挡层的表面处的端接特征和靠近端接特征设置的填充沟槽。填充的沟槽延伸穿过阻挡层以到达衬底层并且被配置为将与掩埋结相关联的电势引导到设置在阻挡层表面附近的端接特征以终止掩埋结。

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