专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06256362B1 Frequency acquisition circuit and method for a phase locked loop 失效
标题翻译：用于锁相环的频率采集电路和方法
公开(公告)号：US06256362B1
公开(公告)日：2001-07-03
申请号：US09107307
申请日：1998-06-30
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H04L700
CPC分类号： H03L7/087 , H03D13/004 , H03L7/085 , H03L7/089 , H04L7/033
摘要： A circuit (14) for aiding proper frequency lock in a phase locked loop (12) includes a phase detector (40) adapted for receiving an input signal and an oscillator output signal from the phase locked loop (12) and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal. An up cycle slip detector (42a) receives the up pulse width modulated cycle slip signal and generates an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal. A down cycle slip detector (42b) receives the down pulse width modulated cycle slip signal and generates a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal. A phase correction circuit (41, 43) is provided for generating a steering signal in response to the up and down cycle slip signals.
摘要翻译：用于辅助锁相环（12）中的适当频率锁定的电路（14）包括适于从锁相环（12）接收输入信号和振荡器输出信号的相位检测器（40），并产生上和下指示输入信号和振荡器输出信号之间的周期滑动的下降脉宽调制信号。上升循环滑差检测器（42a）接收上行脉冲宽度调制循环滑移信号，并产生指示振荡器输出信号滞后于输入信号的上升滑动信号。下降周期滑移检测器（42b）接收向下的脉宽调制周期滑移信号，并产生指示振荡器输出信号在输入信号之前的下降滑动信号。提供相位校正电路（41,43），用于响应于上下周期滑动信号产生转向信号。

2. 发明授权

US06081165A Ring oscillator 失效
标题翻译：环形振荡器
公开(公告)号：US06081165A
公开(公告)日：2000-06-27
申请号：US118473
申请日：1998-07-17
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03K3/03 , H03B27/00
CPC分类号： H03K3/0315
摘要： An improved ring oscillator (10, 70) includes a first, second and third current starved inverters (12, 14, 16) coupled in a ring, a first fast inverter (40) coupled between the second and third current starved inverters (14, 16), and a second fast inverter (45) coupled between the third and first current starved inverters (14, 16). An output buffer (30) coupled to the ring provides an output periodic waveform.
摘要翻译：改进的环形振荡器（10,70）包括耦合在环中的第一，第二和第三电流饥饿逆变器（12,14,16），耦合在第二和第三电流饥饿逆变器（14，14）之间的第一快速逆变器（40） 16）和耦合在第三和第一电流欠缺逆变器（14,16）之间的第二快速逆变器（45）。耦合到环的输出缓冲器（30）提供输出周期波形。

3. 发明授权

US06646420B1 Method of interrupting and dynamically switching ranges to improve battery charge measurement range in a sigma delta converter 有权
标题翻译：在Σ-Δ转换器中断和动态切换范围以改善电池电量测量范围的方法
公开(公告)号：US06646420B1
公开(公告)日：2003-11-11
申请号：US10161349
申请日：2002-05-31
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H01M1044
CPC分类号： H01M10/42 , H01M6/505 , H01M10/488
摘要： A method of improving the battery charge measurement range in a sigma delta converter associated with portable applications such as a cell phone is implemented by interruption of the sigma delta modulator measurement process and changing its reference voltage and measurement time to allow an integrated current to occur over a wider dynamic range.
摘要翻译：在与诸如手机的便携式应用相关联的Σ-Δ转换器中改善电池电荷测量范围的方法通过中和Σ-Δ调制器测量过程并改变其参考电压和测量时间来实现，以允许集成电流发生在更广泛的动态范围。

4. 发明授权

US06466058B1 PLL lock detection using a cycle slip detector with clock presence detection 有权
标题翻译：使用具有时钟存在检测的周期滑移检测器进行PLL锁定检测
公开(公告)号：US06466058B1
公开(公告)日：2002-10-15
申请号：US10016265
申请日：2001-12-10
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03K906
CPC分类号： H03L7/095 , H03L7/089
摘要： A system 400 and method 1400 are disclosed for a lock detection circuit of a phase locked loop used in a communications device. The lock detection circuit includes a cycle slip detector and a clock presence detector. The cycle slip detector receives a reference clock and a VCO feedback clock, and in response to the frequency difference between the reference clock and the VCO feedback clock that remains for a time period greater than the inverse of the frequency difference of the clocks, generates a no cycle slips alarm indication. The no cycle slips alarm status enables the lock detection circuit to provide an indication to the PLL, of the lock condition and whether a cycle slip has occurred. The clock presence detector receives the reference clock and the VCO feedback clock, and in response to determining whether the reference clock or the VCO feedback clock is missing for a time greater than a predetermined count of either remaining clock, generate a no VCO alarm and a no REF alarm indication. The no VCO alarm and the no REF alarm enables the lock detection circuit to provide an alarm indication to the PLL of the presence of the reference clock and the VCO feedback clock.
摘要翻译：公开了用于通信设备中使用的锁相环的锁定检测电路的系统400和方法1400。锁定检测电路包括循环滑移检测器和时钟存在检测器。循环滑移检测器接收参考时钟和VCO反馈时钟，并且响应于参考时钟和保持在大于时钟的频率差的倒数的时间段的VCO反馈时钟之间的频率差，产生无循环滑动报警指示。无循环滑动报警状态使得锁定检测电路能够向PLL提供锁定状态的指示以及是否发生了周期滑移。时钟存在检测器接收参考时钟和VCO反馈时钟，并且响应于确定参考时钟或VCO反馈时钟是否丢失大于剩余时钟的预定计数的时间，产生无VCO报警和无REF报警指示。无VCO报警和无REF报警使锁定检测电路能够向PLL提供参考时钟和VCO反馈时钟的存在的报警指示。

5. 发明申请

US20090167442A1 LOW NOISE WIDE RANGE VOLTAGE-CONTROLLED OSCILLATOR WITH TRANSISTOR FEEDBACK 有权
标题翻译：低噪声宽范围电压控制振荡器，带有晶体管反馈
公开(公告)号：US20090167442A1
公开(公告)日：2009-07-02
申请号：US11968082
申请日：2007-12-31
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03L7/099 , H03K3/03 , H03L7/085
CPC分类号： H03L7/0995 , H03K3/0315 , H03K2005/00026 , H03K2005/00195 , H03L7/183
摘要： An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.
摘要翻译：集成电路，压控振荡器（VCO）和锁相环（PLL）。在一个实施例中，VCO包括：（1）被配置为接收VCO的调谐电压的电压调谐线和（2）奇数个环耦合延迟元件。每个延迟元件包括：（2A）具有耦合到电压调制线的电源线的反相器和（2B）具有增益衰减晶体管的反馈路径，其中栅极耦合到电压调谐线。

6. 发明授权

US06459342B1 System and method for controlling an oscillator 有权
标题翻译：用于控制振荡器的系统和方法
公开(公告)号：US06459342B1
公开(公告)日：2002-10-01
申请号：US09727059
申请日：2000-11-30
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03L7099
CPC分类号： H03L7/099
摘要： An oscillator controls the frequency of an output clock signal in response to detecting an error in the frequency of an input clock signal. The oscillator includes an inverter operable to generate a voltage signal and a resonator coupled to the inverter operable to introduce a phase shift in the voltage signal. The oscillator also includes a variable resistor positioned across a feedback path of the inverter and operable to introduce a further phase shift in the voltage signal in response to the detected error. The resonator is further operable to adjust the frequency of the voltage signal in response to the introduced further phase shift. The voltage signal is used as the output clock signal.
摘要翻译：响应于检测到输入时钟信号的频率的误差，振荡器控制输出时钟信号的频率。振荡器包括可操作以产生电压信号的反相器和耦合到反相器的谐振器，其可操作以在电压信号中引入相移。振荡器还包括位于反相器的反馈路径上的可变电阻器，可操作以响应于检测到的误差而在电压信号中引入进一步的相移。谐振器还可操作以响应于引入的进一步的相移来调整电压信号的频率。电压信号用作输出时钟信号。

7. 发明授权

US08686799B2 Low noise wide range voltage-controlled oscillator with transistor feedback 有权
标题翻译：具有晶体管反馈的低噪声宽范围压控振荡器
公开(公告)号：US08686799B2
公开(公告)日：2014-04-01
申请号：US11968082
申请日：2007-12-31
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K2005/00026 , H03K2005/00195 , H03L7/183
摘要： An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.
摘要翻译：集成电路，压控振荡器（VCO）和锁相环（PLL）。在一个实施例中，VCO包括：（1）被配置为接收VCO的调谐电压的电压调谐线和（2）奇数个环耦合延迟元件。每个延迟元件包括：（2A）具有耦合到电压调制线的电源线的反相器和（2B）具有增益衰减晶体管的反馈路径，其中栅极耦合到电压调谐线。

8. 发明授权

US06931243B2 Fully integrated low noise multi-loop synthesizer with fine frequency resolution for HDD read channel and RF wireless local oscillator applications 有权
标题翻译：全集成低噪声多回路合成器，具有精确的频率分辨率，可用于HDD读取通道和RF无线本地振荡器应用
公开(公告)号：US06931243B2
公开(公告)日：2005-08-16
申请号：US10036831
申请日：2001-12-21
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03L7/12 , H03L7/23 , H04B1/06
CPC分类号： H03L7/23 , H03L7/12
摘要： A low noise multi-loop radio frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune PLL and a coarse tune PLL. The fine tune PLL outputs a fine tune signal with a frequency fR□P, P beings an integer, while the coarse tune PLL outputs a coarse tune signal with frequency fR□A, where A is an integer. A translation PLL has a unity multiplication factor and is driven by the fine tune signal output. The frequency synthesizer has a Gilbert cell double balanced mixer coupled between the coarse tune and the translation PLLs, the Gilbert cell mixer combining the coarse tune signal and the output signal of the translation PLL and coupling the mixed signal into the translation PLL. The translation loop outputs a signal with a frequency proportional to the linear sum of the coarse tune signal and the fine tune signal.
摘要翻译：低噪声多环射频合成器将具有频率f R R的输入参考信号接收到微调PLL和粗调PLL中。微调PLL输出具有频率f L R P P的微调信号，P是一个整数，而粗调PLL输出具有频率f R R / □A，其中A是整数。翻译PLL具有单位乘法因子，并由微调信号输出驱动。频率合成器具有耦合在粗调和转换PLL之间的吉尔伯特单元双平衡混频器，吉尔伯特单元混频器组合粗调信号和平移PLL的输出信号，并将混合信号耦合到平移PLL。平移环路输出具有与粗调信号和微调信号的线性和成正比的频率的信号。

9. 发明授权

US06611176B1 Method and apparatus for two zeros/two poles active compensation phase locked loops 有权
标题翻译：用于两个零/二极有源补偿锁相环的方法和装置
公开(公告)号：US06611176B1
公开(公告)日：2003-08-26
申请号：US09745985
申请日：2000-12-21
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03L7093
CPC分类号： H03L7/093 , H03L7/18 , Y10S331/02
摘要： A phase locked loop with two zeros/two poles active compensation. The two poles and two zeros provide increased stability with capability for narrow bandwidth and the active component (such as operational amplifier) provides increased gain and higher noise immunity. Schematic diagrams of exemplary and preferred embodiments, design assumptions, and associated equations are disclosed. Other assumptions and equations are within the scope of the invention, provided the disclosed format for an open loop voltage transfer function for two zeros/two poles is maintained.
摘要翻译：具有两个零/二极点的锁相环有源补偿。这两个极点和两个零点对于窄带宽提供了更高的稳定性，并且有源分量（例如运算放大器）提供增加的增益和更高的抗噪声能力。公开了示例性和优选实施例，设计假设和相关方程的示意图。其他假设和方程都在本发明的范围内，只要保持用于两个零/二极的开环电压传递函数的公开格式即可。

10. 发明授权

US07639070B2 Switching circuit in a phase locked loop (PLL) to minimize current leakage in integrated circuits 有权
标题翻译：开关电路采用锁相环（PLL），以最大限度地减少集成电路中的电流泄漏
公开(公告)号：US07639070B2
公开(公告)日：2009-12-29
申请号：US12020691
申请日：2008-01-28
申请人： Stanley J. Goldman
发明人： Stanley J. Goldman
IPC分类号： H03B1/00 , H03K5/00 , H04B1/10
CPC分类号： H03L7/093 , H03K2005/00293 , H03L7/0891 , Y10T156/1761
摘要： In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of differential input signals and provide a pair of differential output signals. A timing control circuit controls a pair of switches, the pair of switches being operable to conduct the pair of differential output signals in response to at least one signal of the pair of differential input signals being present. An operational amplifier (OA) includes a pair of OA input terminals and an OA output terminal. The pair of OA input terminals is coupled to receive the pair of differential output signals conducted by the pair of switches. A feedback circuit is coupled between the OA output terminal and a first one of the pair of OA input terminals. The pair of switches is disabled by the timing control circuit to block a current leakage from the feedback circuit.
摘要翻译：在用于减少锁相环（PLL）中的电流泄漏的装置和方法中，耦合一对电阻分压器电路以接收一对差分输入信号并提供一对差分输出信号。定时控制电路控制一对开关，所述一对开关可操作以响应于所述一对差分输入信号中的至少一个信号而导通所述一对差分输出信号。运算放大器（OA）包括一对OA输入端子和OA输出端子。这对OA输入端子被耦合以接收由该对开关传导的一对差分输出信号。反馈电路耦合在OA输出端和一对OA输入端中的第一个之间。定时控制电路禁用该对开关，以阻止来自反馈电路的电流泄漏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式