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1. 发明授权

US6107824A Circuitry and methods for internal interconnection of programmable logic devices 失效
公开(公告)号：US6107824A
公开(公告)日：2000-08-22
申请号：US86302
申请日：1998-05-28
申请人： Srinivas T. Reddy , Ketan Zaveri , Christopher F. Lane , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen , Manuel Mejia , Richard G. Cliff
发明人： Srinivas T. Reddy , Ketan Zaveri , Christopher F. Lane , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen , Manuel Mejia , Richard G. Cliff
IPC分类号： H03K19/177 , G06F7/38 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17792
摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

2. 发明授权

US06335634B1 Circuitry and methods for internal interconnection of programmable logic devices 有权
标题翻译：可编程逻辑器件内部互连的电路和方法
公开(公告)号：US06335634B1
公开(公告)日：2002-01-01
申请号：US09577297
申请日：2000-05-22
申请人： Srinivas T. Reddy , Ketan Zaveri , Christopher F. Lane , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen , Manuel Mejia , Richard G. Cliff
发明人： Srinivas T. Reddy , Ketan Zaveri , Christopher F. Lane , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen , Manuel Mejia , Richard G. Cliff
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/17792
摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.
摘要翻译：提供了用于在可编程逻辑器件上选择性地互连逻辑的可编程互连组布置。互连组可以被编程为在设备上的各种导体之间路由信号，并且将信号从设备上的各种逻辑区域路由到各种导体。互连组提供路由灵活性和效率，而不需要使用过多的互连资源。

3. 发明授权

US6157210A Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits 失效
公开(公告)号：US6157210A
公开(公告)日：2000-12-05
申请号：US082867
申请日：1998-05-21
申请人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
发明人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
IPC分类号： G01R31/3185 , G06F7/38 , C01D1/32
CPC分类号： G01R31/318516
摘要： A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

4. 发明授权

US06897678B2 Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits 失效
标题翻译：具有用于观察可编程逻辑电路信号和用于预加载可编程逻辑电路的电路的可编程逻辑器件
公开(公告)号：US06897678B2
公开(公告)日：2005-05-24
申请号：US10255661
申请日：2002-09-25
申请人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
发明人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： G01R31/318516
摘要： A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.
摘要翻译：提供了一种可编程逻辑器件，其包含电路，该电路可用于观察器件上来自可编程逻辑电路的逻辑信号，以测试器件的操作。还提供了可用于将数据预加载到设备上的各种电路中的电路。逻辑信号观察电路可以允许观察注册的信号，可以允许观察组合信号，或者允许观察到注册信号和组合信号。

5. 发明授权

US06481000B1 Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits 有权
标题翻译：具有用于观察可编程逻辑电路信号和用于预加载可编程逻辑电路的电路的可编程逻辑器件
公开(公告)号：US06481000B1
公开(公告)日：2002-11-12
申请号：US09608061
申请日：2000-06-29
申请人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
发明人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
IPC分类号： G06F1750
CPC分类号： G01R31/318516
摘要： A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.
摘要翻译：提供了一种可编程逻辑器件，其包含电路，该电路可用于观察器件上来自可编程逻辑电路的逻辑信号，以测试器件的操作。还提供了可用于将数据预加载到设备上的各种电路中的电路。逻辑信号观察电路可以允许观察注册的信号，可以允许观察组合信号，或者允许观察到注册信号和组合信号。

6. 发明授权

US06215326B1 Programmable logic device architecture with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06215326B1
公开(公告)日：2001-04-10
申请号：US09266235
申请日：1999-03-10
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

7. 发明授权

US06879183B2 Programmable logic device architectures with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06879183B2
公开(公告)日：2005-04-12
申请号：US10260712
申请日：2002-09-27
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

8. 发明授权

US5977793A Programmable logic device with hierarchical interconnection resources 失效
公开(公告)号：US5977793A
公开(公告)日：1999-11-02
申请号：US855192
申请日：1997-05-13
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H01L21/82 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1778
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

9. 发明授权

US06798242B2 Programmable logic device with hierarchical interconnection resources 失效
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06798242B2
公开(公告)日：2004-09-28
申请号：US10426991
申请日：2003-04-29
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

10. 发明授权

US06577160B2 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06577160B2
公开(公告)日：2003-06-10
申请号：US10170026
申请日：2002-06-10
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联。本地导体与每个区域相关联。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

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