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    • 4. 发明授权
    • Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same
    • 在集成电路器件中形成精细图案的方法以及包括其的集成电路器件的制造方法
    • US08247291B2
    • 2012-08-21
    • US13009298
    • 2011-01-19
    • Jae-Ho MinYoung-Ju ParkMyeong-Cheol Kim
    • Jae-Ho MinYoung-Ju ParkMyeong-Cheol Kim
    • H01L21/74
    • H01L27/11526H01L21/0337H01L21/0338H01L21/28132H01L21/31144H01L21/76816H01L27/11529
    • A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.
    • 一种制造集成电路器件的方法包括在基片的相应的第一和第二区域的硬掩模层上形成第一和第二预掩模结构。 间隔件形成在第一和第二预掩模结构的相对侧壁上,并且第一预备掩模结构从第一区域中的间隔物之间​​选择性地去除。 使用间隔物和第二预备掩模结构作为掩模蚀刻硬掩模层,以限定包括在第一区域中具有空隙的相对的侧壁间隔物的第一掩模图案,以及包括相对的侧壁间隔件和第二掩模图案的第二掩模图案 在第二区域之间的初步掩模结构。 使用第一和第二掩模图案作为相应的掩模来图案化绝缘层,以限定第一区域中的第一沟槽和第二区域中的第二沟槽具有比第一沟槽更大的宽度,并且第一和第二导电图案形成在 第一和第二个沟渠。
    • 5. 发明申请
    • METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME
    • 在集成电路装置中形成精细图案的方法和制造包括其中的集成电路装置的方法
    • US20110183505A1
    • 2011-07-28
    • US13009298
    • 2011-01-19
    • Jae-Ho MinYoung-Ju ParkMyeong-Cheol Kim
    • Jae-Ho MinYoung-Ju ParkMyeong-Cheol Kim
    • H01L21/28
    • H01L27/11526H01L21/0337H01L21/0338H01L21/28132H01L21/31144H01L21/76816H01L27/11529
    • A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.
    • 一种制造集成电路器件的方法包括在基片的相应的第一和第二区域的硬掩模层上形成第一和第二预掩模结构。 间隔件形成在第一和第二预掩模结构的相对侧壁上,并且第一预备掩模结构从第一区域中的间隔物之间​​选择性地去除。 使用间隔物和第二预备掩模结构作为掩模蚀刻硬掩模层,以限定包括在第一区域中具有空隙的相对的侧壁间隔物的第一掩模图案,以及包括相对的侧壁间隔件和第二掩模图案的第二掩模图案 在第二区域之间的初步掩模结构。 使用第一和第二掩模图案作为相应的掩模来图案化绝缘层,以限定第一区域中的第一沟槽和第二区域中的第二沟槽具有比第一沟槽更大的宽度,并且第一和第二导电图案形成在 第一和第二个沟渠。
    • 6. 发明申请
    • FABRICATING METHOD OF SEMICONDUCTOR DEVICE
    • 半导体器件制造方法
    • US20140273432A1
    • 2014-09-18
    • US13841132
    • 2013-03-15
    • BYUNG-HEE KIMTae-Soo KimSeong-Ho ParkYoung-Ju ParkJu-Young Jung
    • BYUNG-HEE KIMTae-Soo KimSeong-Ho ParkYoung-Ju ParkJu-Young Jung
    • H01L21/768
    • H01L21/76816H01L21/31144
    • A semiconductor device is fabricated by forming a lower conductor in a first interlayer dielectric film. A second interlayer dielectric film is formed on the lower conductor and the first interlayer dielectric film. A first hard mask pattern is formed on the second interlayer dielectric film. The first mask pattern has a first opening extending in a first direction. A planarization layer is formed on the first hard mask pattern. A mask pattern is formed on the planarization layer. The mask pattern has a second opening extending in a second direction perpendicular to the first direction. The lower conductor is positioned under an region where the first opening and the second opening overlap. A via hole and a trench connected to the via hole is formed using the first hard mask pattern and the mask pattern. The via hole exposes an upper surface of the lower conductor.
    • 通过在第一层间电介质膜中形成下导体来制造半导体器件。 第二层间电介质膜形成在下导体和第一层间电介质膜上。 在第二层间电介质膜上形成第一硬掩模图案。 第一掩模图案具有沿第一方向延伸的第一开口。 在第一硬掩模图案上形成平坦化层。 在平坦化层上形成掩模图案。 掩模图案具有沿垂直于第一方向的第二方向延伸的第二开口。 下导体位于第一开口和第二开口重叠的区域的下方。 使用第一硬掩模图案和掩模图案形成通孔和连接到通孔的沟槽。 通孔露出下导体的上表面。