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1. 发明申请

US20070126719A1 Aging pad and flat panel display device having the same 有权
标题翻译：老化垫和具有相同功能的平板显示装置
公开(公告)号：US20070126719A1
公开(公告)日：2007-06-07
申请号：US11473137
申请日：2006-06-23
申请人： Soon-Kwang Hong , Young-Ju Park
发明人： Soon-Kwang Hong , Young-Ju Park
IPC分类号： G09G5/00
CPC分类号： G02F1/136204 , G02F1/1345 , G02F1/13458 , G02F2001/136254
摘要： A flat panel display device includes: a display panel; a driving circuit unit for applying a drive signal to the display panel; and a plurality of aging pads connected with the driving circuit unit and applying aging signals to the display panel, wherein each aging pad includes a plurality of sub-aging pads.
摘要翻译：平板显示装置包括：显示面板; 驱动电路单元，用于向显示面板施加驱动信号; 以及与所述驱动电路单元连接并且将陈旧信号施加到所述显示面板的多个老化垫，其中每个老化垫包括多个次老化垫。

2. 发明授权

US07872644B2 Aging pad and flat panel display device having the same 有权
标题翻译：老化垫和具有相同功能的平板显示装置
公开(公告)号：US07872644B2
公开(公告)日：2011-01-18
申请号：US11473137
申请日：2006-06-23
申请人： Soon-Kwang Hong , Young-Ju Park
发明人： Soon-Kwang Hong , Young-Ju Park
IPC分类号： G09G5/00 , G09G3/10 , G09G3/30
CPC分类号： G02F1/136204 , G02F1/1345 , G02F1/13458 , G02F2001/136254
摘要： A flat panel display device includes: a display panel; a driving circuit unit for applying a drive signal to the display panel; and a plurality of aging pads connected with the driving circuit unit and applying aging signals to the display panel, wherein each aging pad includes a plurality of sub-aging pads.
摘要翻译：平板显示装置包括：显示面板; 驱动电路单元，用于向显示面板施加驱动信号; 以及与所述驱动电路单元连接并且将陈旧信号施加到所述显示面板的多个老化垫，其中每个老化垫包括多个次老化垫。

3. 发明申请

US20090246966A1 Method of fine patterning semiconductor device 有权
标题翻译：精细图案化半导体器件的方法
公开(公告)号：US20090246966A1
公开(公告)日：2009-10-01
申请号：US12217782
申请日：2008-07-09
申请人： Nam-Myun Cho , Myeong-Cheol Kim , Shi-Yong Yi , Young-Hoon Song , Young-Ju Park
发明人： Nam-Myun Cho , Myeong-Cheol Kim , Shi-Yong Yi , Young-Hoon Song , Young-Ju Park
IPC分类号： H01L21/308
CPC分类号： H01L21/02118 , H01L21/02282 , H01L21/0337 , H01L21/3086 , H01L21/31058 , H01L21/312 , H01L21/32139 , H01L27/105 , H01L27/1052
摘要： For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a portion of the mask material in the second area, and the mask material is patterned to form spacers on sidewalls of the spacer support structure and to form a mask pattern under the masking structure. The spacer support structure and the masking structure are comprised of respective high carbon content materials that have been spin-coated and have substantially a same etch selectivity.
摘要翻译：对于集成电路制造，在半导体衬底上的第一区域中形成至少一个间隔件支撑结构，并且掩模材料沉积在间隔件支撑结构的暴露表面上并在半导体衬底上的第二区域上。在第二区域中的掩模材料的一部分上形成掩模结构，并且掩模材料被图案化以在间隔物支撑结构的侧壁上形成间隔物，并在掩模结构下方形成掩模图案。间隔物支撑结构和掩蔽结构由已经旋涂并具有基本上相同蚀刻选择性的相应的高碳含量材料构成。

4. 发明授权

US08247291B2 Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same 有权
标题翻译：在集成电路器件中形成精细图案的方法以及包括其的集成电路器件的制造方法
公开(公告)号：US08247291B2
公开(公告)日：2012-08-21
申请号：US13009298
申请日：2011-01-19
申请人： Jae-Ho Min , Young-Ju Park , Myeong-Cheol Kim
发明人： Jae-Ho Min , Young-Ju Park , Myeong-Cheol Kim
IPC分类号： H01L21/74
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/31144 , H01L21/76816 , H01L27/11529
摘要： A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.
摘要翻译：一种制造集成电路器件的方法包括在基片的相应的第一和第二区域的硬掩模层上形成第一和第二预掩模结构。间隔件形成在第一和第二预掩模结构的相对侧壁上，并且第一预备掩模结构从第一区域中的间隔物之间选择性地去除。使用间隔物和第二预备掩模结构作为掩模蚀刻硬掩模层，以限定包括在第一区域中具有空隙的相对的侧壁间隔物的第一掩模图案，以及包括相对的侧壁间隔件和第二掩模图案的第二掩模图案在第二区域之间的初步掩模结构。使用第一和第二掩模图案作为相应的掩模来图案化绝缘层，以限定第一区域中的第一沟槽和第二区域中的第二沟槽具有比第一沟槽更大的宽度，并且第一和第二导电图案形成在第一和第二个沟渠。

5. 发明申请

US20110183505A1 METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME 有权
标题翻译：在集成电路装置中形成精细图案的方法和制造包括其中的集成电路装置的方法
公开(公告)号：US20110183505A1
公开(公告)日：2011-07-28
申请号：US13009298
申请日：2011-01-19
申请人： Jae-Ho Min , Young-Ju Park , Myeong-Cheol Kim
发明人： Jae-Ho Min , Young-Ju Park , Myeong-Cheol Kim
IPC分类号： H01L21/28
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/31144 , H01L21/76816 , H01L27/11529
摘要： A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.
摘要翻译：一种制造集成电路器件的方法包括在基片的相应的第一和第二区域的硬掩模层上形成第一和第二预掩模结构。间隔件形成在第一和第二预掩模结构的相对侧壁上，并且第一预备掩模结构从第一区域中的间隔物之间选择性地去除。使用间隔物和第二预备掩模结构作为掩模蚀刻硬掩模层，以限定包括在第一区域中具有空隙的相对的侧壁间隔物的第一掩模图案，以及包括相对的侧壁间隔件和第二掩模图案的第二掩模图案在第二区域之间的初步掩模结构。使用第一和第二掩模图案作为相应的掩模来图案化绝缘层，以限定第一区域中的第一沟槽和第二区域中的第二沟槽具有比第一沟槽更大的宽度，并且第一和第二导电图案形成在第一和第二个沟渠。

6. 发明申请

US20140273432A1 FABRICATING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20140273432A1
公开(公告)日：2014-09-18
申请号：US13841132
申请日：2013-03-15
申请人： BYUNG-HEE KIM , Tae-Soo Kim , Seong-Ho Park , Young-Ju Park , Ju-Young Jung
发明人： BYUNG-HEE KIM , Tae-Soo Kim , Seong-Ho Park , Young-Ju Park , Ju-Young Jung
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/31144
摘要： A semiconductor device is fabricated by forming a lower conductor in a first interlayer dielectric film. A second interlayer dielectric film is formed on the lower conductor and the first interlayer dielectric film. A first hard mask pattern is formed on the second interlayer dielectric film. The first mask pattern has a first opening extending in a first direction. A planarization layer is formed on the first hard mask pattern. A mask pattern is formed on the planarization layer. The mask pattern has a second opening extending in a second direction perpendicular to the first direction. The lower conductor is positioned under an region where the first opening and the second opening overlap. A via hole and a trench connected to the via hole is formed using the first hard mask pattern and the mask pattern. The via hole exposes an upper surface of the lower conductor.
摘要翻译：通过在第一层间电介质膜中形成下导体来制造半导体器件。第二层间电介质膜形成在下导体和第一层间电介质膜上。在第二层间电介质膜上形成第一硬掩模图案。第一掩模图案具有沿第一方向延伸的第一开口。在第一硬掩模图案上形成平坦化层。在平坦化层上形成掩模图案。掩模图案具有沿垂直于第一方向的第二方向延伸的第二开口。下导体位于第一开口和第二开口重叠的区域的下方。使用第一硬掩模图案和掩模图案形成通孔和连接到通孔的沟槽。通孔露出下导体的上表面。

7. 发明申请

US20120080723A1 FABRICATING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME METHOD 审中-公开
标题翻译：使用相同方法制作的半导体器件和半导体器件的制造方法
公开(公告)号：US20120080723A1
公开(公告)日：2012-04-05
申请号：US13213364
申请日：2011-08-19
申请人： Jin-Wook LEE , Myeong-Cheol Kim , Sang-Min Lee , Young-Ju Park , Hyung-Yong Kim , Myung-Hoon Jung
发明人： Jin-Wook LEE , Myeong-Cheol Kim , Sang-Min Lee , Young-Ju Park , Hyung-Yong Kim , Myung-Hoon Jung
IPC分类号： H01L21/336 , H01L21/28 , H01L29/78 , H01L21/3065
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/30608 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L27/11 , H01L29/66636 , H01L29/78
摘要： A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.
摘要翻译：半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开，在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域，同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。

8. 发明授权

US06534385B2 Method of fusion for heteroepitaxial layers and overgrowth thereon 失效
公开(公告)号：US06534385B2
公开(公告)日：2003-03-18
申请号：US10003999
申请日：2001-11-14
申请人： Young-Ju Park , Sung-Min Hwang , Eun-Kyu Kim
发明人： Young-Ju Park , Sung-Min Hwang , Eun-Kyu Kim
IPC分类号： H01L2130
CPC分类号： H01L21/76251 , H01L21/02381 , H01L21/02392 , H01L21/02463 , H01L21/02494 , H01L21/02546 , H01L21/02658 , H01L21/2007 , H01L21/76248
摘要： The present invention relates to a method of fusion for heteroepitaxial layers and overgrowth thereon. According to the present invention, a high quality heteroepilayer can be formed by patterning a fused semiconductor layer, overgrowing it with a persistent patterned character, and fusing other semiconductors having different lattice constants by means of utilizing the rate difference between the lateral growth rate and the vertical growth rate exhibited, on the above process. Further, according to the present invention, the lattice constant difference of the two semiconductors can be overcome and a high quality quantum structure can be formed. According to the present invention, the junction of two semiconductor materials having different lattice constants, as well as a good overgrowth on heteroepitaxial layers can be carried out. Accordingly to the present invention, the base material from which the new, as yet on realized, conceptive optoelectronic device can be made.

9. 发明授权

US08592265B2 Method for manufacturing semiconductor device having a metal gate electrode 有权
标题翻译：具有金属栅电极的半导体器件的制造方法
公开(公告)号：US08592265B2
公开(公告)日：2013-11-26
申请号：US13242382
申请日：2011-09-23
申请人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
发明人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
IPC分类号： H01L21/338
CPC分类号： H01L21/28132 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
摘要翻译：示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚设栅电极的一部分形成第一凹槽，所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部第二个凹槽

10. 发明申请

US20120088359A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120088359A1
公开(公告)日：2012-04-12
申请号：US13242382
申请日：2011-09-23
申请人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
发明人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
摘要翻译：示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚拟栅电极的一部分形成第一凹槽，所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部第二个凹槽

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