专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09768163B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US09768163B2
公开(公告)日：2017-09-19
申请号：US14744722
申请日：2015-06-19
申请人： Doo-Young Lee , Sang-Hyun Lee , Myung-Hoon Jung , Do-Hyoung Kim
发明人： Doo-Young Lee , Sang-Hyun Lee , Myung-Hoon Jung , Do-Hyoung Kim
IPC分类号： H01L27/088 , H01L29/45 , H01L21/768 , H01L21/28 , H01L29/417 , H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/11
CPC分类号： H01L27/088 , H01L21/28114 , H01L21/76804 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L27/0207 , H01L27/0886 , H01L27/1104 , H01L29/41758 , H01L29/41775 , H01L29/45 , H01L29/78
摘要： A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

2. 发明授权

US09755079B2 Semiconductor devices including insulating gates and methods for fabricating the same 有权
公开(公告)号：US09755079B2
公开(公告)日：2017-09-05
申请号：US15000495
申请日：2016-01-19
申请人： Sang-Jine Park , Keun-Hee Bai , Kyoung-Hwan Yeo , Bo-Un Yoon , Kee-Sang Kwon , Do-Hyoung Kim , Ha-Young Jeon , Seung-Seok Ha
发明人： Sang-Jine Park , Keun-Hee Bai , Kyoung-Hwan Yeo , Bo-Un Yoon , Kee-Sang Kwon , Do-Hyoung Kim , Ha-Young Jeon , Seung-Seok Ha
IPC分类号： H01L27/088 , H01L29/78 , H01L29/49 , H01L29/423 , H01L29/06 , H01L27/092 , H01L27/12
CPC分类号： H01L29/785 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0657 , H01L29/4238 , H01L29/495 , H01L29/7848
摘要： Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

3. 发明授权

US09543155B2 Method of forming minute patterns and method of manufacturing a semiconductor device using the same 有权
标题翻译：形成微小图案的方法和使用其制造半导体器件的方法
公开(公告)号：US09543155B2
公开(公告)日：2017-01-10
申请号：US14975932
申请日：2015-12-21
申请人： Bok-Young Lee , Yoo-Jung Lee , Dong-Hoon Khang , Do-Hyoung Kim , Cheol Kim , In-Hee Lee , Ji-Eun Han
发明人： Bok-Young Lee , Yoo-Jung Lee , Dong-Hoon Khang , Do-Hyoung Kim , Cheol Kim , In-Hee Lee , Ji-Eun Han
IPC分类号： H01L21/28 , H01L29/66 , H01L27/11
CPC分类号： H01L21/28132 , H01L27/1104 , H01L27/1116 , H01L29/66545
摘要： A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.
摘要翻译：一种方法包括在衬底上形成第一蚀刻目标层和第一掩模层。在第一方向上在第一掩模层上形成沿第一方向延伸的牺牲图案。垫片形成在牺牲图案的侧壁上。在去除牺牲图案之后，使用间隔件作为蚀刻掩模来蚀刻第一掩模层以形成第一掩模。第二掩模形成在每个第一掩模的侧壁上以限定包括每个第一掩模的第三掩模和在每个第一掩模的侧壁上的第二掩模。使用第一和第三掩模蚀刻第一蚀刻目标层作为蚀刻掩模，以分别在第一和第二区域中形成第一和第二图案。每个第一图案具有第一宽度，并且每个第二图案具有大于第一宽度的第二宽度。

4. 发明申请

US20160315085A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160315085A1
公开(公告)日：2016-10-27
申请号：US15049648
申请日：2016-02-22
申请人： Yong-Joon CHOI , Tae-Yong KWON , Mirco CANTORO , Chang-Jae YANG , Dong-Hoon KHANG , Woo-Ram KIM , Cheol KIM , Seung-Jin MUN , Seung-Mo HA , Do-Hyoung KIM , Seong-Ju KIM , So-Ra YOU , Woong-ki HONG
发明人： Yong-Joon CHOI , Tae-Yong KWON , Mirco CANTORO , Chang-Jae YANG , Dong-Hoon KHANG , Woo-Ram KIM , Cheol KIM , Seung-Jin MUN , Seung-Mo HA , Do-Hyoung KIM , Seong-Ju KIM , So-Ra YOU , Woong-ki HONG
IPC分类号： H01L27/092 , H01L29/16 , H01L29/165 , H01L29/06
CPC分类号： H01L27/0924 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/1104 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.
摘要翻译：半导体器件包括化合物半导体层，其中化合物半导体层在分开的区域中包括单独的鳍状图案。单独的翅片图案可以包括不同的材料。单独的翅片图案可以包括不同的尺寸，包括鳍片图案的一个或多个部分的宽度和高度中的一个或多个。单独的翅片图案可以包括上图案和下图案。上部图案和下部图案可以包括不同的材料。上部图案和下部图案可以包括不同的尺寸。单独的区域可以包括NMOS或PMOS的单独区域。半导体器件可以包括化合物半导体层上的栅电极。单独的栅电极可以与分开的鳍片图案相交。

5. 发明申请

US20160307803A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20160307803A1
公开(公告)日：2016-10-20
申请号：US15083248
申请日：2016-03-28
申请人： Seung-Jin MUN , Dong-Hoon KHANG , Woo-Ram KIM , Cheol KIM , Dong-Seok LEE , Yong-Joon CHOI , Seung-Mo HA , Do-Hyoung KIM
发明人： Seung-Jin MUN , Dong-Hoon KHANG , Woo-Ram KIM , Cheol KIM , Dong-Seok LEE , Yong-Joon CHOI , Seung-Mo HA , Do-Hyoung KIM
IPC分类号： H01L21/8234 , H01L21/308
CPC分类号： H01L21/823431 , H01L21/3086 , H01L23/544 , H01L2223/54426 , H01L2223/54453
摘要： A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.
摘要翻译：制造半导体器件的方法可以包括在包括第一区域和第二区域的衬底上形成牺牲层，在第二区域的牺牲层上形成第一图案，在第一区域的牺牲层上形成第二图案在所述第二图案的相对侧壁上形成第一上隔片，去除所述第二图案，使用所述第一上隔片作为蚀刻掩模蚀刻所述第一区域的所述第一牺牲层以形成第三图案，蚀刻所述第二图案的所述第一牺牲层区域，使用第一图案作为蚀刻掩模以形成第四图案，在第三图案的任一侧形成第一下隔片，在第四图案的相对侧壁上形成第二间隔物，去除第三图案和第四图案，并蚀刻使用第一下隔板和第二间隔件作为蚀刻掩模。

6. 发明申请

US20160181425A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20160181425A1
公开(公告)日：2016-06-23
申请号：US14959457
申请日：2015-12-04
申请人： Keun Hee BAI , Kyoung Hwan YEO , Seung Seok HA , Seung Ju PARK , Do Hyoung KIM , Myeong Cheol KIM , Jae Hyoung KOO , Ki Byung PARK
发明人： Keun Hee BAI , Kyoung Hwan YEO , Seung Seok HA , Seung Ju PARK , Do Hyoung KIM , Myeong Cheol KIM , Jae Hyoung KOO , Ki Byung PARK
IPC分类号： H01L29/78 , H01L29/165 , H01L29/161 , H01L29/66 , H01L29/06
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66545 , H01L29/66818 , H01L29/7851
摘要： There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.
摘要翻译：提供了一种制造半导体器件的方法，该半导体器件包括：包括多个有源区的衬底;沿第一方向延伸以与多个有源区的一部分相交的多个栅电极，并且包括设置到在第一方向上彼此相邻，设置在第一和第二栅极之间的栅极隔离部分。栅极隔离部分包括在垂直于第一方向的第二方向上设置在第一层的两端上的第一层和第二层。

7. 发明申请

US20160163718A1 SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN 审中-公开
公开(公告)号：US20160163718A1
公开(公告)日：2016-06-09
申请号：US15047181
申请日：2016-02-18
申请人： Sang-Jine Park , Kee-Sang Kwon , Do-Hyoung Kim , Bo-Un Yoon , Keun-Hee Bai , Kwang-Yong Yang , Kyoung-Hwan Yeo , Yong-Ho Jeon
发明人： Sang-Jine Park , Kee-Sang Kwon , Do-Hyoung Kim , Bo-Un Yoon , Keun-Hee Bai , Kwang-Yong Yang , Kyoung-Hwan Yeo , Yong-Ho Jeon
IPC分类号： H01L27/11 , H01L29/08 , H01L29/06 , H01L29/161 , H01L29/165 , H01L29/78 , H01L27/092 , H01L29/16
CPC分类号： H01L27/1104 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L27/0924 , H01L27/1116 , H01L29/06 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/7848
摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

8. 外观设计

USD644761S1 LED lamp 有权
公开(公告)号：USD644761S1
公开(公告)日：2011-09-06
申请号：US29382053
申请日：2010-12-28
申请人： Seong Jin Lee , Ki Tae Kang , Do Hyoung Kim
设计人： Seong Jin Lee , Ki Tae Kang , Do Hyoung Kim

9. 发明申请

US20090030181A1 Peptides for Inhibiting MDM2 Function 有权
标题翻译：抑制MDM2功能的肽
公开(公告)号：US20090030181A1
公开(公告)日：2009-01-29
申请号：US11547730
申请日：2004-12-29
申请人： Kyou-Hoon Han , Seung-Wook Chi , Hyun-Jeong Kim , Si-Hyung Lee , Min-Jung Ahn , Do-Hyoung Kim , Jae-Sung Kim , Shin-Ae Park
发明人： Kyou-Hoon Han , Seung-Wook Chi , Hyun-Jeong Kim , Si-Hyung Lee , Min-Jung Ahn , Do-Hyoung Kim , Jae-Sung Kim , Shin-Ae Park
IPC分类号： C07K7/06 , C07K5/08 , C07K5/10
CPC分类号： C07K14/4746
摘要： Disclosed are peptides for inhibiting mdm2 (mouse double minute 2) and a pharmaceutical composition comprising the same.
摘要翻译：公开了抑制mdm2（小鼠双倍分子2）的肽和包含其的药物组合物。

10. 发明授权

US07145872B1 Method for managing system resources in network system in which digital interface is used for connection 失效
标题翻译：用于管理数字接口用于连接的网络系统中的系统资源的方法
公开(公告)号：US07145872B1
公开(公告)日：2006-12-05
申请号：US09624348
申请日：2000-07-24
申请人： Do-hyoung Kim
发明人： Do-hyoung Kim
IPC分类号： H04J3/16 , H04N7/173
CPC分类号： H04L12/40058 , H04L12/40065 , H04L12/40117 , H04L2012/563 , H04L2012/5632 , H04L2012/5636 , H04Q11/0478
摘要： A method for managing system resources in a network system in which a digital interface is used for connection is provided. The method for managing system resources required for communication between a source device and a sink device includes the steps of (a) initially allocating system resources presently required to the source device, (b) monitoring the format of the output bit stream of the source device in a state in which communication between the two devices is maintained, (c) allocating additional system resources to the source device or releasing redundant system resources from the source device, under the lead of the source device when it is determined as a result of monitoring that the requirements for system resources have changed, and (d) detecting final system resources and releasing the detected system resources when communication between two devices is terminated.
摘要翻译：提供一种用于管理数字接口用于连接的网络系统中的系统资源的方法。用于管理源设备和宿设备之间的通信所需的系统资源的方法包括以下步骤：（a）初始分配源设备当前所需的系统资源，（b）监视源设备的输出比特流的格式在维持两个设备之间的通信的状态下，（c）在源设备的引导下，当确定作为监视的结果时，向源设备分配额外的系统资源或从源设备释放冗余系统资源系统资源的需求发生变化，（d）终止两台设备之间的通信时，检测最终的系统资源和释放检测到的系统资源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式