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    • 2. 发明专利
      JP2013179671A Signal interleaving for the serial clock and data recovery 审中-公开
    • Signal interleaving for the serial clock and data recovery
    • 用于串行时钟和数据恢复的信号交互
    • JP2013179671A
    • 2013-09-09
    • JP2013098761
    • 2013-05-08
    • Silicon Image Inc , シリコン イメージ,インコーポレイテッド
    • LEE DONGYUN , KIM SUNGJOON
    • H04L7/02 , H03L7/08 , H04L25/08 , H04L25/40
    • H04L7/0337 , H03L7/07 , H03L7/0812
    • PROBLEM TO BE SOLVED: To provide a clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream.SOLUTION: The CDR system (100) comprises a sampling circuit (105) that produces a recovered clock/data signal; and an interleaving feedback network (110). The feedback network comprises: a logic circuit (115) that produces control signals based on the recovered signal; a first multiplexer (120) that selects from four phases of a global clock signal based on a control signal; a first delay-locked loop (130) having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal; and a second delay-locked loop (135) having a second set of delay cells that produces a set of phase-shifted feedback signals.
    • 要解决的问题：提供一种用于从串行数据流中恢复定时信息和数据的时钟和数据恢复（CDR）系统和方法。解决方案：CDR系统（100）包括采样电路（105），其产生恢复的时钟 /数据信号; 和交织反馈网络（110）。 反馈网络包括：逻辑电路（115），其基于恢复的信号产生控制信号; 第一多路复用器（120），其基于控制信号从全局时钟信号的四相中选择; 第一延迟锁定环路（130），具有耦合到第二多路复用器的第一组延迟单元，其基于所选择的全局时钟信号产生延迟的信号; 以及具有产生一组相移反馈信号的第二组延迟单元的第二延迟锁定环路（135）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明专利
      JP2008099303A Signal interleaving for serial clock and data recovery 有权
    • Signal interleaving for serial clock and data recovery
    • 用于串行时钟和数据恢复的信号交互
    • JP2008099303A
    • 2008-04-24
    • JP2007275730
    • 2007-09-25
    • Silicon Image Inc , シリコン イメージ,インコーポレイテッド
    • LEE DONGYUN , KIM SUNGJOON
    • H04L7/02 , H03L7/081 , H04L25/40
    • H04L7/0337 , H03L7/07 , H03L7/0812
    • PROBLEM TO BE SOLVED: To provide a clock and data recovery (CRD) system and method that recovers timing information and data from a serial data stream. SOLUTION: A CDR system (100) has a sampling circuit (105) generating a clock/data signal that is in a recovery state, and an interleaving feedback network (110). This network has a logic circuit (115) generating a control signal based on a recovery signal, a first multiplexer (120) selecting from four phases of a global clock signal based on the control signal, a first delay locked loop (130) including a first set of delay cells coupled to a second multiplexer that generates a delay signal based on the selected global clock signal, and a second delay locked loop (135) including a second set of delay cells that generates a set of phase-shifted feedback signals. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题：提供从串行数据流恢复定时信息和数据的时钟和数据恢复（CRD）系统和方法。 解决方案：CDR系统（100）具有产生处于恢复状态的时钟/数据信号的采样电路（105）和交织反馈网络（110）。 该网络具有基于恢复信号产生控制信号的逻辑电路（115），第一多路复用器（120）基于控制信号从全局时钟信号的四相中选择第一延迟锁定环（130），包括 耦合到第二多路复用器的第一组延迟单元，其基于所选择的全局时钟信号产生延迟信号，以及包括产生一组相移反馈信号的第二组延迟单元的第二延迟锁定环路（135）。 版权所有（C）2008，JPO＆INPIT
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明专利
      AU7202496A Transition-controlled digital encoding and signal transmission system 未知
    • Transition-controlled digital encoding and signal transmission system
    • AU7202496A
    • 1997-04-28
    • AU7202496
    • 1996-09-30
    • SILICON IMAGE INC
    • SHIN YESHIK , LEE KYEONGHO , KIM SUNGJOON , LEE DAVID D
    • H03M7/14 , H04L7/00 , H04L7/04 , H04L25/03 , H04L25/08 , H04L25/49 , H04N7/083 , H04N7/52 , H03M5/14
    • A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明专利
      CA2233906A1 TRANSITION-CONTROLLED DIGITAL ENCODING AND SIGNAL TRANSMISSION SYSTEM 未知
    • TRANSITION-CONTROLLED DIGITAL ENCODING AND SIGNAL TRANSMISSION SYSTEM
    • CA2233906A1
    • 1997-04-10
    • CA2233906
    • 1996-09-30
    • SILICON IMAGE INC
    • KIM SUNGJOON , LEE KYEONGHO , SHIN YESHIK , LEE DAVID D
    • H03M7/14 , H04L7/00 , H04L7/04 , H04L25/03 , H04L25/08 , H04L25/49 , H04N7/083 , H04N7/52 , H03M7/00 , H04L25/00 , H04L25/02 , H04N5/38
    • A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明申请
      WO2007115227A3 MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 审中-公开
    • MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS
    • 具有可变端口速度的多端口存储器件
    • WO2007115227A3
    • 2007-11-29
    • PCT/US2007065723
    • 2007-03-30
    • SILICON IMAGE INC , LEE DONGYUN , CHO MYUNG RAI , KIM SUNGJOON
    • LEE DONGYUN , CHO MYUNG RAI , KIM SUNGJOON
    • G11C7/10 , G11C8/16
    • G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
    • A multi-port memory device (100) having two or more ports (110) wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock (SCK) and a port clock (PCK). The system clock is applied to port logic (220) that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit (230) that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
    • 具有两个或多个端口（110）的多端口存储器件（100），其中每个端口可以以不同的速度操作。 多端口存储器件包含可通过两个或更多个端口访问的存储体。 两个时钟信号施加到每个端口：系统时钟（SCK）和端口时钟（PCK）。 系统时钟被应用于与存储体接口的端口逻辑（220），使得端口都以相对于存储体的公共速度运行。 端口时钟被施加到与每个端口相关联的时钟分频器电路（230）。 端口时钟被分为所需频率或保持在其原始频率。 这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明专利
      CA2233906C TRANSITION-CONTROLLED DIGITAL ENCODING AND SIGNAL TRANSMISSION SYSTEM 未知
    • TRANSITION-CONTROLLED DIGITAL ENCODING AND SIGNAL TRANSMISSION SYSTEM
    • CA2233906C
    • 2005-09-20
    • CA2233906
    • 1996-09-30
    • SILICON IMAGE INC
    • LEE KYEONGHO , KIM SUNGJOON , SHIN YESHIK , LEE DAVID D
    • H03M7/14 , H04L7/00 , H04L7/04 , H04L25/03 , H04L25/08 , H04L25/49 , H04N7/083 , H04N7/52 , H03M7/00 , H04L25/00 , H04L25/02 , H04N5/38
    • A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectivel y complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemente d data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one o f the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined numb er of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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