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1. 发明申请

WO2007115226A3 INTER-PORT COMMUNICATION IN A MULTI- PORT MEMORY DEVICE 审中-公开
标题翻译：多端口存储器中的端口间通信
公开(公告)号：WO2007115226A3
公开(公告)日：2008-10-30
申请号：PCT/US2007065722
申请日：2007-03-30
申请人： SILICON IMAGE INC , RUBERG ALAN , KIM DAE K , SHIM DAEYUN , LEE DONGYUN , CHO MYUNG RAI , KIM SUNGJOON
发明人： RUBERG ALAN , KIM DAE K , SHIM DAEYUN , LEE DONGYUN , CHO MYUNG RAI , KIM SUNGJOON
IPC分类号： G06F15/167
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.
摘要翻译：一种利用多端口存储设备的端口间通信的方法和系统。存储器件包含中断寄存器，中断信号接口（例如，专用引脚），中断掩码以及与每个端口相关联的一个或多个消息缓冲器。当耦合到存储器件的第一端口的第一部件想要与耦合到存储器件的第二端口的第二部件通信时，第一部件将消息写入与第二端口相关联的消息缓冲器。第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。在接收到中断时，第二个组件读取中断寄存器以确定中断的性质。然后第二个组件从消息缓冲区读取消息。

2. 发明申请

WO2007115227A2 MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 审中-公开
标题翻译：具有可变端口速度的多端口存储器件
公开(公告)号：WO2007115227A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/065723
申请日：2007-03-30
申请人： SILICON IMAGE, INC. , LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
发明人： LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
IPC分类号： G11C7/10 , G11C8/16
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
摘要翻译：具有两个或多个端口的多端口存储器件，其中每个端口可以以不同的速度操作。多端口存储器件包含可通过两个或更多个端口访问的存储体。每个端口都应用两个时钟信号：系统时钟和端口时钟。系统时钟被应用于与存储体接口的端口逻辑，使得端口都以相对于存储体的公共速度运行。端口时钟应用于与每个端口相关联的时钟分频器电路。端口时钟被分为所需频率或保持在其原始频率。这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

3. 发明申请

WO2007115227A3 MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 审中-公开
标题翻译：具有可变端口速度的多端口存储器件
公开(公告)号：WO2007115227A3
公开(公告)日：2007-11-29
申请号：PCT/US2007065723
申请日：2007-03-30
申请人： SILICON IMAGE INC , LEE DONGYUN , CHO MYUNG RAI , KIM SUNGJOON
发明人： LEE DONGYUN , CHO MYUNG RAI , KIM SUNGJOON
IPC分类号： G11C7/10 , G11C8/16
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A multi-port memory device (100) having two or more ports (110) wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock (SCK) and a port clock (PCK). The system clock is applied to port logic (220) that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit (230) that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
摘要翻译：具有两个或多个端口（110）的多端口存储器件（100），其中每个端口可以以不同的速度操作。多端口存储器件包含可通过两个或更多个端口访问的存储体。两个时钟信号施加到每个端口：系统时钟（SCK）和端口时钟（PCK）。系统时钟被应用于与存储体接口的端口逻辑（220），使得端口都以相对于存储体的公共速度运行。端口时钟被施加到与每个端口相关联的时钟分频器电路（230）。端口时钟被分为所需频率或保持在其原始频率。这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

4. 发明申请

WO2012033289A3 SENSOR FOR SENSING THE END OF THE LOWER THREAD OF A SEWING MACHINE, AND LOWER THREAD BOBBIN 审中-公开
标题翻译：用于感应缝纫机下方螺纹的传感器，以及较低的螺纹BOBBIN
公开(公告)号：WO2012033289A3
公开(公告)日：2012-05-31
申请号：PCT/KR2011005902
申请日：2011-08-11
申请人： BOBBINTEL INC , CHO MYUNG RAI
发明人： CHO MYUNG RAI
IPC分类号： D05B59/02 , D05B57/26
CPC分类号： D05B51/00 , D05B57/28 , D05B59/00 , D05B59/02
摘要： The present invention relates to a sensor for sensing the end of a lower thread of a sewing machine, which senses that the lower thread is completely spent during a sewing process, to thereby prevent degradation in quality and reworking due to idle backstitching. The sensor includes: a lower thread end sensor photo controller that contacts a lower thread wound around a lower thread bobbin in order to activate or deactivate a light-emitting function, a light-reflecting function, a light-passing or light-transmitting function, and/or a light-blocking function through a physical locomotion operation in accordance with unwinding of the end of the lower thread; a light receiver that receives light emitted by the operation of the lower thread end sensor photo controller, in order to output a sensing signal; and a control notification device that analyzes the sensing signal outputted by the light receiver in order to determine that the end of the lower thread is unwound, and outputs a result of the determination to a user.
摘要翻译：本发明涉及一种用于感测缝纫机底线端部的传感器，其感测到在缝纫过程中底线完全消耗，从而防止质量下降和由于空闲背缝引起的返工。传感器包括：下螺纹端传感器光控制器，其接触卷绕在下线轴上的下线，以激活或去激发发光功能，光反射功能，光通过或透光功能，和/或通过根据所述底线末端展开的物理运动操作的遮光功能; 接收由所述下线端传感器光控制器的操作发出的光的光接收器，以输出感测信号; 以及控制通知装置，其分析由光接收器输出的感测信号，以便确定底线的端部展开，并将确定的结果输出给用户。

5. 发明申请

WO2012033288A3 SENSOR FOR SENSING THE END OF THE LOWER THREAD OF A SEWING MACHINE 审中-公开
标题翻译：用于感应缝纫机下方螺纹的传感器
公开(公告)号：WO2012033288A3
公开(公告)日：2012-05-31
申请号：PCT/KR2011005900
申请日：2011-08-11
申请人： BOBBINTEL INC , CHO MYUNG RAI
发明人： CHO MYUNG RAI
IPC分类号： D05B59/02 , D05B59/00
CPC分类号： D05B59/02
摘要： The present invention relates to a sensor for sensing the end of a lower thread of a sewing machine, which senses that the lower thread is completely spent during a sewing process, to thereby prevent degradation in quality and reworking due to idle backstitching. The sensor includes: a lower thread end sensor switch that contacts the end of a lower thread wound around a lower thread bobbin so as to turn an electrical contact on or off in accordance with the unwinding of the end of the lower thread; a sensing signal transmitter that transmits a sensing signal for notifying that the end of the lower thread is unwound according to the operation of the lower thread end sensor switch; and a control notification device that receives the sensing signal from the sensing signal transmitter and analyzes same to determine that the end of the lower thread is unwound, and outputs the result of the determination to a user.
摘要翻译：本发明涉及一种用于感测缝纫机底线端部的传感器，其感测到在缝纫过程中底线完全消耗，从而防止质量下降和由于空闲背缝引起的返工。传感器包括：下螺纹末端传感器开关，其接触卷绕在下线轴上的下线的端部，以便根据底线端部的展开来打开或关闭电触头; 感测信号发送器，其根据所述下线端传感器开关的操作发送用于通知所述下线的端部退绕的感测信号; 以及控制通知装置，其从感测信号发送器接收感测信号，并对其进行分析，以确定下线的末端解卷，并将确定结果输出给用户。

6. 发明申请

WO2007115226A2 INTER-PORT COMMUNICATION IN A MULTI- PORT MEMORY DEVICE 审中-公开
标题翻译：多端口存储器中的端口间通信
公开(公告)号：WO2007115226A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/065722
申请日：2007-03-30
申请人： SILICON IMAGE, INC. , RUBERG, Alan , KIM, Dae, K. , SHIM, Daeyun , LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
发明人： RUBERG, Alan , KIM, Dae, K. , SHIM, Daeyun , LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.
摘要翻译：一种利用多端口存储器件进行端口间通信的方法和系统。存储器件包含中断寄存器，中断信号接口（例如，专用引脚），中断掩码以及与每个端口相关联的一个或多个消息缓冲器。当耦合到存储设备的第一端口的第一组件想要与耦合到存储器设备的第二端口的第二组件通信时，第一组件将消息写入与第二端口相关联的消息缓冲器。第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。在接收到中断时，第二个组件读取中断寄存器以确定中断的性质。然后第二个组件从消息缓冲区读取消息。

7. 发明申请

WO2007115229A1 SHARED NONVOLATILE MEMORY ARCHITECTURE 审中-公开
标题翻译：共享非易失性存储器架构
公开(公告)号：WO2007115229A1
公开(公告)日：2007-10-11
申请号：PCT/US2007/065727
申请日：2007-03-30
申请人： SILICON IMAGE, INC. , CHO, Myung, Rai , LEE, Dongyun , RUBERG, Alan
发明人： CHO, Myung, Rai , LEE, Dongyun , RUBERG, Alan
IPC分类号： G06F9/445
CPC分类号： G06F15/177 , G06F9/4405
摘要： A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.
摘要翻译：一种利用共享非易失性存储器来初始化设备中的多个处理组件的方法和系统。用于处理设备内的组件的启动逻辑和配置数据存储在单个非易失性存储器中。在接收到用于初始化设备的命令时，共享存储器系统将启动逻辑和配置数据从非易失性存储器复制到易失性主存储器。然后，每个处理组件访问主存储器以找到其启动逻辑和配置数据并开始执行。共享存储器系统减少用于初始化多个处理组件的非易失性存储器组件的数量。

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