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1. 发明专利

JP2008160858A Current mode circuitry to modulate common mode voltage 有权
标题翻译：电流模式电路来调节共模电压
公开(公告)号：JP2008160858A
公开(公告)日：2008-07-10
申请号：JP2007341857
申请日：2007-12-20
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SHIM DAEYUN , KIM MIN-KYU , KIM GYUDONG , JUNG KEEWOOK , HWANG SEUNG HO
IPC分类号： H04L25/02 , H03K17/687 , H03K19/0175 , H03K19/094 , H03K19/0952
CPC分类号： H04L5/20
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit with transmitters to transmit differential signals on conductors and current mode circuitry selectively to modulate a common mode voltage of the differential signals, so as to communicate data. SOLUTION: A system includes a first integrated circuit to transmit first and second differential signals on conductors, and a second integrated circuit. The second integrated circuit includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and the current mode circuitry selectively to modulate a common mode voltage of either the first or second differential signals to communicate data. Here, the first integrated circuit includes a common mode detection circuitry and detects changes in the common mode voltage. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有发射机的集成电路，用于选择性地在导体和电流模式电路上传输差分信号，以调制差分信号的共模电压，以便传送数据。解决方案：系统包括用于在导体上传输第一和第二差分信号的第一集成电路和第二集成电路。第二集成电路包括接收器，用于接收来自导体的第一和第二差分信号并提供表示其的接收信号，并且电流模式电路选择性地调制第一或第二差分信号的共模电压以传送数据。这里，第一集成电路包括共模检测电路并检测共模电压的变化。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2009219159A Method for combining clock signal and data signal 有权
标题翻译：用于组合时钟信号和数据信号的方法
公开(公告)号：JP2009219159A
公开(公告)日：2009-09-24
申请号：JP2009153903
申请日：2009-06-29
申请人： Silicon Image Inc , シリコン・イメージ,インコーポレーテッド
发明人： KIM GYUDONG , KIM OOK , KIM MINKYU , KIM BRUCE , HWANG SEUNG HO
IPC分类号： H03L7/099 , H04L7/04 , G09G5/00 , H04L5/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L25/49
CPC分类号： H04L25/4902 , G09G5/006 , H04L5/06 , H04L7/0008 , H04L7/0054 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To provide a method for transmitting data in a system including at least one data channel and a separate clock channel. SOLUTION: This method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal is generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a leading edge and a trailing edge, and the data signal is modulated for the clock signal by moving at least one edge (i.e., leading or trailing edge or both) of the plurality of pulses, thereby creating a combined clock and data signal. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。解决方案：该方法涉及将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。在一个实施例中，使用将数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成数据信号。在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且通过移动至少一个边缘（即，前沿或后沿或两者）来调制数据信号以用于时钟信号多个脉冲，从而产生组合的时钟和数据信号。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2002359613A METHOD FOR COMBINING CLOCK SIGNAL AND DATA SIGNAL 审中-公开
公开(公告)号：JP2002359613A
公开(公告)日：2002-12-13
申请号：JP2002075003
申请日：2002-03-18
申请人： SILICON IMAGE INC
发明人： KIM GYUDONG , KIM OOK , KIM MINKYU , KIM BRUCE , HWANG SEUNG HO
IPC分类号： H03L7/099 , G09G5/00 , H04L5/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/04 , H04L25/49
摘要： PROBLEM TO BE SOLVED: To provide a method of transmitting data in a system including at least one data channel and a separate clock channel. SOLUTION: This method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e., front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

4. 发明专利

CA2396948A1 A SYSTEM AND METHOD FOR SENDING AND RECEIVING DATA SIGNALS OVER A CLOCK SIGNAL LINE 未知
公开(公告)号：CA2396948A1
公开(公告)日：2002-05-16
申请号：CA2396948
申请日：2001-10-30
申请人： SILICON IMAGE INC
发明人： KIM MIN-KYU , KIM GYUDONG , HWANG SEUNG HO
IPC分类号： G06F13/38 , G06F1/12 , H04L1/12 , H04L7/00 , H04L7/04 , H04L25/02 , H04L25/38 , H04L25/00
摘要： The system preferably includes a unique transmitter that sends both clock an d data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extrac t data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a returm channel encoder. The clock re-generator monitors t he transmission line, receives signals, filters them and generates a clock sign al at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

5. 发明专利

CA2471536A1 SYSTEM FOR REGENERATING A CLOCK FOR DATA TRANSMISSION 未知
公开(公告)号：CA2471536A1
公开(公告)日：2003-07-17
申请号：CA2471536
申请日：2002-12-05
申请人： SILICON IMAGE INC
发明人： BANKS JOHN D , SFARTI ADRIAN , SIEMENS DUANE , KEATING STEPHEN J , JUNG KEEWOOK , WOLF PAUL DANIEL , LEE ERIC , AHN GIJUNG , SCALISE ALBERT M , HWANG SEUNG HO
IPC分类号： H04N7/04 , G09G5/00 , H04J3/00 , H04L1/00 , H04L1/20 , H04L25/49 , H04N5/12 , H04N7/045 , H04N19/89 , H04N21/233 , H04N21/236 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/434 , H04N7/08 , H04N7/52
摘要： A communication system (Fig. 2) including a transmitter (1'), a receiver (2'), and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter (1') to the receiver (2'). The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels (CH0, CH1, CH2) of the link during data islands between burst of encoded video data, a pixel clock is transmitted over the link, and the receiver (2') regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.

6. 发明专利

CA2466463A1 METHOD AND SYSTEM FOR VIDEO AND AUXILIARY DATA TRANSMISSION OVER A SERIAL LINK 未知
公开(公告)号：CA2466463A1
公开(公告)日：2003-07-17
申请号：CA2466463
申请日：2002-12-05
申请人： SILICON IMAGE INC
发明人： KEATING STEPHEN J , SIEMENS DUANE , BANKS JOHN D , WOLF PAUL DANIEL , JUNG KEEWOOK , LYLE JAMES D , AHN GIJUNG , GREKHOV VLADIMIR , HWANG SEUNG HO , SCHUMACHER MICHAEL ANTHONY , SCALISE ALBERT M , LEE ERIC
IPC分类号： H04N7/08 , H04L1/00 , H04L1/20 , H04L9/20 , H04L25/49 , H04N20060101 , H04N1/00 , H04N7/081 , H04N7/52 , H04N7/66
摘要： A communication system including a transmitter (1~), a receiver (2~), and a serial link, in transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one of more channels of the link during data islands between bursts of encoded video dat a. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

7. 发明专利

CA2309519A1 METHODS AND SYSTEMS FOR TMDS ENCRYPTION 未知
公开(公告)号：CA2309519A1
公开(公告)日：2000-11-28
申请号：CA2309519
申请日：2000-05-26
申请人： SILICON IMAGE INC
发明人： KIM GYUDONG , DA COSTA VICTOR M , MARTIN RUSSEL A , HWANG SEUNG HO , LEE DAVID D , KIM BRUCE
IPC分类号： H04L9/34
摘要： The present invention is directed io systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of a) performing transition controlled encoding of a fast sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+l bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.

8. 发明申请

WO0016525A8 A SYSTEM AND METHOD FOR SENDING AND RECEIVING DATA SIGNALS OVER A CLOCK SIGNAL LINE 审中-公开
标题翻译：用于发送和接收时钟信号线上的数据信号的系统和方法
公开(公告)号：WO0016525A8
公开(公告)日：2001-03-08
申请号：PCT/US9920488
申请日：1999-09-10
申请人： SILICON IMAGE INC
发明人： KIM GYUDONG , KIM MIN-KYU , HWANG SEUNG HO
IPC分类号： H04J3/06 , H04L7/00 , H04L25/49 , H04L29/04 , H04L25/02
CPC分类号： G09G5/006 , G09G5/008 , G09G2370/04 , H04L7/0008 , H04L25/4902
摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock and data signal provided by the transmitter.
摘要翻译：该系统优选地包括在同一传输线上发送时钟和数据信号的唯一发射机。接收机使用相同的传输线将数据信号发送回发射机。发射机包括时钟发生器，解码器和线路接口。时钟发生器产生包括可变位置下降沿的时钟信号。下降沿位置被接收器解码以从时钟信号中提取数据。接收机包括时钟再生器，数据解码器和返回通道编码器。时钟再发生器监视传输线，接收信号，对它们进行滤波，并在接收机上根据传输线上的信号产生时钟信号。返回通道编码器产生信号并在传输线上断言它们。信号由发射机提供的时钟和数据信号断言或叠加。

9. 发明申请

WO2004023268A3 METHOD AND APPARATUS FOR DOUBLE DATA RATE SERIAL ATA PHY INTERFACE 审中-公开
标题翻译：用于双数据速率串行ATA PHY接口的方法和设备
公开(公告)号：WO2004023268A3
公开(公告)日：2004-06-03
申请号：PCT/US0328121
申请日：2003-09-08
申请人： SILICON IMAGE INC
发明人： KIM OOK , KIM SUNGJOON , NORMAN ROBERT , HO CHI WAI , LEE FRANK , LEE DONGYUN , AHN GIJUNG , HWANG SEUNG HO
IPC分类号： G06F20060101 , G06F3/00 , G06F13/38 , G06F13/40 , H04J3/06
CPC分类号： G06F13/385 , G06F13/4022
摘要： A method for multiplexing (130) control signals for disk drives includes developing parallel control signals and developing serial control signals. At least one of the parallel control signals and the serial control signals are coupled to at least one of a parallel hard disk drive (50,60) and a serial hard disk drive (80, 90) by a common control bus.
摘要翻译：用于多路复用（130）磁盘驱动器的控制信号的方法包括开发并行控制信号并产生串行控制信号。并行控制信号和串行控制信号中的至少一个通过公共控制总线耦合到并行硬盘驱动器（50,60）和串行硬盘驱动器（80,90）中的至少一个。

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