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1. 发明专利

JP2009219159A Method for combining clock signal and data signal 有权
标题翻译：用于组合时钟信号和数据信号的方法
公开(公告)号：JP2009219159A
公开(公告)日：2009-09-24
申请号：JP2009153903
申请日：2009-06-29
申请人： Silicon Image Inc , シリコン・イメージ,インコーポレーテッド
发明人： KIM GYUDONG , KIM OOK , KIM MINKYU , KIM BRUCE , HWANG SEUNG HO
IPC分类号： H03L7/099 , H04L7/04 , G09G5/00 , H04L5/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L25/49
CPC分类号： H04L25/4902 , G09G5/006 , H04L5/06 , H04L7/0008 , H04L7/0054 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To provide a method for transmitting data in a system including at least one data channel and a separate clock channel. SOLUTION: This method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal is generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a leading edge and a trailing edge, and the data signal is modulated for the clock signal by moving at least one edge (i.e., leading or trailing edge or both) of the plurality of pulses, thereby creating a combined clock and data signal. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。解决方案：该方法涉及将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。在一个实施例中，使用将数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成数据信号。在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且通过移动至少一个边缘（即，前沿或后沿或两者）来调制数据信号以用于时钟信号多个脉冲，从而产生组合的时钟和数据信号。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2007215213A System and method for multiple-phase clock generation 审中-公开
标题翻译：多相时钟生成系统与方法
公开(公告)号：JP2007215213A
公开(公告)日：2007-08-23
申请号：JP2007065275
申请日：2007-03-14
申请人： Silicon Image Inc , シリコン・イメージ,インコーポレーテッド
发明人： KIM OOK , LI HUNG SUNG , LEE INYEOL , KIM GYUDONG , LEE YONGMAN
IPC分类号： H03K5/15 , G06F1/06 , H03K21/00 , H03K23/00 , H03K23/54 , H03L7/089 , H03L7/099
CPC分类号： H03K23/542 , G06F1/06 , H03K5/15013 , H03L7/0891 , H03L7/0995
摘要： PROBLEM TO BE SOLVED: To provide a method for multiple-phase clock generation. SOLUTION: In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired number of clock phase outputs. The clock divider (304) in this embodiment includes a state machine, e.g., a modified Johnson counter (316), that provides a plurality of divided down clock phases, each of which is connected to separate modified shift registers (306-314). Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment, the number of clock phase outputs of the multiple-phase clock is a function which multiplies the number of VCO clock phases by the number of desired states in the modified Johnson counter. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于多相时钟产生的方法。解决方案：在一个实施例中，多级压控振荡器（“VCO”）302将多个时钟相位（ck0-ck5）发送到产生期望数量的时钟相位的时钟分频器（304）输出。本实施例中的时钟分频器（304）包括状态机，例如经修改的约翰逊计数器（316），其提供多个划分的下降时钟相位，每个相位分别与分离的修改的移位寄存器（306-314）连接。每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。在一个实施例中，多相时钟的时钟相位输出的数量是将VCO时钟相位数乘以经修改的约翰逊计数器中的期望状态的数量的函数。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2008160858A Current mode circuitry to modulate common mode voltage 有权
标题翻译：电流模式电路来调节共模电压
公开(公告)号：JP2008160858A
公开(公告)日：2008-07-10
申请号：JP2007341857
申请日：2007-12-20
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SHIM DAEYUN , KIM MIN-KYU , KIM GYUDONG , JUNG KEEWOOK , HWANG SEUNG HO
IPC分类号： H04L25/02 , H03K17/687 , H03K19/0175 , H03K19/094 , H03K19/0952
CPC分类号： H04L5/20
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit with transmitters to transmit differential signals on conductors and current mode circuitry selectively to modulate a common mode voltage of the differential signals, so as to communicate data. SOLUTION: A system includes a first integrated circuit to transmit first and second differential signals on conductors, and a second integrated circuit. The second integrated circuit includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and the current mode circuitry selectively to modulate a common mode voltage of either the first or second differential signals to communicate data. Here, the first integrated circuit includes a common mode detection circuitry and detects changes in the common mode voltage. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有发射机的集成电路，用于选择性地在导体和电流模式电路上传输差分信号，以调制差分信号的共模电压，以便传送数据。解决方案：系统包括用于在导体上传输第一和第二差分信号的第一集成电路和第二集成电路。第二集成电路包括接收器，用于接收来自导体的第一和第二差分信号并提供表示其的接收信号，并且电流模式电路选择性地调制第一或第二差分信号的共模电压以传送数据。这里，第一集成电路包括共模检测电路并检测共模电压的变化。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2002359613A METHOD FOR COMBINING CLOCK SIGNAL AND DATA SIGNAL 审中-公开
公开(公告)号：JP2002359613A
公开(公告)日：2002-12-13
申请号：JP2002075003
申请日：2002-03-18
申请人： SILICON IMAGE INC
发明人： KIM GYUDONG , KIM OOK , KIM MINKYU , KIM BRUCE , HWANG SEUNG HO
IPC分类号： H03L7/099 , G09G5/00 , H04L5/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/04 , H04L25/49
摘要： PROBLEM TO BE SOLVED: To provide a method of transmitting data in a system including at least one data channel and a separate clock channel. SOLUTION: This method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e., front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

5. 发明专利

JP2014075803A Method, apparatus, and system for pre-authentication and processing of data streams 有权
标题翻译：数据流预认证和处理的方法，装置和系统
公开(公告)号：JP2014075803A
公开(公告)日：2014-04-24
申请号：JP2013230239
申请日：2013-11-06
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： CHOI HOON , KIM GYUDONG , KIM WOOK , LYLE JAMES D , ALEXANDER PEYSAKHOVICH , MICHAEL SCHUMACHER , SHIM DAEYUN
IPC分类号： H04N21/4363 , G06F21/44
CPC分类号： H04L63/0876 , G09G5/006 , G09G2370/12 , G11B20/00086 , G11B20/00463 , H04N5/4401 , H04N5/913 , H04N7/1675 , H04N21/2541 , H04N21/4122 , H04N21/4367 , H04N21/4408 , H04N21/835
摘要： PROBLEM TO BE SOLVED: To provide a method, apparatus and system for pre-authenticating ports.SOLUTION: In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in an idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so that the pre-authenticated inactive ports can subsequently replace the active port when a port switch is performed.
摘要翻译：要解决的问题：提供一种用于对端口进行预认证的方法，装置和系统。解决方案：在一个实施例中，识别出在发送设备和接收设备之间促进媒体内容的通信的活动端口，而活动端口被关联与第一个高清内容保护（HDCP）引擎。然后，标识处于空闲模式的用作备用端口到活动端口的非活动端口，而非活动端口与第二HDCP引擎相关联。执行每个非活动端口的预认证，使得在执行端口交换机时，预认证的非活动端口可以随后替换活动端口。

6. 发明专利

JP2014060778A Method, apparatus and system for constructing and facilitating mobile high-definition multimedia interface 有权
标题翻译：用于构建和促进移动高清晰度多媒体接口的方法，装置和系统
公开(公告)号：JP2014060778A
公开(公告)日：2014-04-03
申请号：JP2013236708
申请日：2013-11-15
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： KIM GYUDONG , SUNG BAEGIN , CHOI HOON
IPC分类号： H04N21/436 , H04J3/06 , H04L5/22 , H04L25/02
CPC分类号： G06F3/14 , G06F13/4072 , G09G5/006 , G09G2370/045 , G09G2370/047 , H04L65/605
摘要： PROBLEM TO BE SOLVED: To provide a method, apparatus and system for constructing and facilitating a Mobile High-Definition Multimedia Interface.SOLUTION: In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to construct a mobile high-definition interface. The mobile high-definition interface is configured to facilitate transmission of high-definition media content between mobile devices. The apparatus further includes a receiver coupled with the transmitter. The receiver is configured to receive the single channel and to unmerge the single channel into the multiple channels.
摘要翻译：要解决的问题：提供一种用于构建和促进移动高分辨率多媒体接口的方法，装置和系统。解决方案：在一个实施例中，一种装置包括：发射机，被配置为将高清晰度接口的多个信道合并为单个渠道构建移动高清接口。移动高清晰度接口被配置为便于在移动设备之间传输高清晰度媒体内容。该装置还包括与发射机耦合的接收机。接收器被配置为接收单个信道并且将单个信道解除合并到多个信道中。

7. 发明专利

JP2007129735A Clock edge modulated serial link including dc balance control 有权
标题翻译：时钟边缘调制串行链路，包括直流平衡控制
公开(公告)号：JP2007129735A
公开(公告)日：2007-05-24
申请号：JP2006322567
申请日：2006-10-31
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： KIM GYUDONG , CHOE WON JUN , JEONG DEOG-KYOON , KIM JAEHA , LEE BONG-JOON , KIM MIN-KYU
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： PROBLEM TO BE SOLVED: To provide a serial channel for supporting clocks, data and control signals such as DC balancing control signals to a low power mobile device. SOLUTION: A battery powered computing device has a channel arranged as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is arranged to apply clock edge modulated signals to the channel, wherein the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is arranged to recover the direct current balancing control signals. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于向低功率移动设备支持诸如DC平衡控制信号的时钟，数据和控制信号的串行通道。解决方案：电池供电的计算设备具有排列成单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射机被布置成将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被布置成恢复直流平衡控制信号。版权所有（C）2007，JPO＆INPIT

8. 发明专利

AT533301T 未知
公开(公告)号：AT533301T
公开(公告)日：2011-11-15
申请号：AT09714761
申请日：2009-02-26
申请人： SILICON IMAGE INC
发明人： CHOI HOON , KIM GYUDONG , KIM OOK , LYLE JAMES , PEYSAKHOVICH ALEXANDER , SCHUMACHER MICHAEL , SHIM DAEYUN
IPC分类号： H04N5/44

9. 发明专利

AT452370T 未知
公开(公告)号：AT452370T
公开(公告)日：2010-01-15
申请号：AT04754870
申请日：2004-06-10
申请人： SILICON IMAGE INC
发明人： KIM OOK , LEE ERIC , KIM GYUDONG , JANG ZEEHOON , SUNG BAEGIN , KIM NAM , AHN GIJUNG , HWANG SEUNG
IPC分类号： G06F13/38 , G06F13/00
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.

10. 发明专利

CA2441967A1 SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION 未知
公开(公告)号：CA2441967A1
公开(公告)日：2002-10-17
申请号：CA2441967
申请日：2002-04-09
申请人： SILICON IMAGE INC
发明人： LEE YONGMAN , LEE INYEOL , KIM GYUDONG , LI HUNG SUNG , KIM OOK
IPC分类号： G06F1/06 , H03K5/15 , H03K23/00 , H03K23/54 , H03L7/089 , H03L7/099 , H03K19/00
摘要： Published without an

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