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1. 发明专利

JP5053484B2 Bidirectional data transmission using the video blanking interval of the digital data stream 有权
公开(公告)号：JP5053484B2
公开(公告)日：2012-10-17
申请号：JP2000569306
申请日：1999-09-09
申请人：シリコン・イメージ,インコーポレーテッド
发明人：マーティン，ラッセル，エイ
IPC分类号： G06F3/153 , H04N7/173 , G09G5/00 , H04N7/083
CPC分类号： G09G5/006 , G09G2370/04 , H04N7/083 , H04N11/042
摘要： Digital pixel data is transferred from a computer system to video display hardware in a forward direction. However, there are many reasons for digital pixel data to be transferred in both directions along a cable connecting a computer and a monitor. This invention describes a method of sending digital data from a monitor back to the computer in a reverse direction. In transmission of digital pixel data in a forward direction, there are horizontal and vertical blanking periods during which special characters are transmitted in order to resynchronize the digital pixel data to a clock signal. In such a system the transmission of these special characters only requires a portion of the blanking periods. During the remainder to the blanking period, some of or all of the data paths can be used in order to transmit digital data in a reverse direction. Where all data paths are used, the beginning and end of the usable portion of the blanking periods may last for a fixed number of clock cycles. Alternatively, the beginning and end of the usable portion of the blanking periods may be indicated by signals transmitted in a forward direction over one of the data paths, where all data paths are not used in a reverse direction.

2. 发明专利

JP2009219159A Method for combining clock signal and data signal 有权
标题翻译：用于组合时钟信号和数据信号的方法
公开(公告)号：JP2009219159A
公开(公告)日：2009-09-24
申请号：JP2009153903
申请日：2009-06-29
申请人： Silicon Image Inc , シリコン・イメージ,インコーポレーテッド
发明人： KIM GYUDONG , KIM OOK , KIM MINKYU , KIM BRUCE , HWANG SEUNG HO
IPC分类号： H03L7/099 , H04L7/04 , G09G5/00 , H04L5/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L25/49
CPC分类号： H04L25/4902 , G09G5/006 , H04L5/06 , H04L7/0008 , H04L7/0054 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To provide a method for transmitting data in a system including at least one data channel and a separate clock channel. SOLUTION: This method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal is generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a leading edge and a trailing edge, and the data signal is modulated for the clock signal by moving at least one edge (i.e., leading or trailing edge or both) of the plurality of pulses, thereby creating a combined clock and data signal. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。解决方案：该方法涉及将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。在一个实施例中，使用将数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成数据信号。在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且通过移动至少一个边缘（即，前沿或后沿或两者）来调制数据信号以用于时钟信号多个脉冲，从而产生组合的时钟和数据信号。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2007215213A System and method for multiple-phase clock generation 审中-公开
标题翻译：多相时钟生成系统与方法
公开(公告)号：JP2007215213A
公开(公告)日：2007-08-23
申请号：JP2007065275
申请日：2007-03-14
申请人： Silicon Image Inc , シリコン・イメージ,インコーポレーテッド
发明人： KIM OOK , LI HUNG SUNG , LEE INYEOL , KIM GYUDONG , LEE YONGMAN
IPC分类号： H03K5/15 , G06F1/06 , H03K21/00 , H03K23/00 , H03K23/54 , H03L7/089 , H03L7/099
CPC分类号： H03K23/542 , G06F1/06 , H03K5/15013 , H03L7/0891 , H03L7/0995
摘要： PROBLEM TO BE SOLVED: To provide a method for multiple-phase clock generation. SOLUTION: In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired number of clock phase outputs. The clock divider (304) in this embodiment includes a state machine, e.g., a modified Johnson counter (316), that provides a plurality of divided down clock phases, each of which is connected to separate modified shift registers (306-314). Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment, the number of clock phase outputs of the multiple-phase clock is a function which multiplies the number of VCO clock phases by the number of desired states in the modified Johnson counter. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于多相时钟产生的方法。解决方案：在一个实施例中，多级压控振荡器（“VCO”）302将多个时钟相位（ck0-ck5）发送到产生期望数量的时钟相位的时钟分频器（304）输出。本实施例中的时钟分频器（304）包括状态机，例如经修改的约翰逊计数器（316），其提供多个划分的下降时钟相位，每个相位分别与分离的修改的移位寄存器（306-314）连接。每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。在一个实施例中，多相时钟的时钟相位输出的数量是将VCO时钟相位数乘以经修改的约翰逊计数器中的期望状态的数量的函数。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP3895544B2 System and method for high-speed synchronous data communication 有权
公开(公告)号：JP3895544B2
公开(公告)日：2007-03-22
申请号：JP2000509195
申请日：1998-09-04
申请人：シリコン・イメージ,インコーポレーテッド
发明人：アーン，ギジュン , ジェオン，デオ−キョン
IPC分类号： H04L25/40 , H04L7/033
CPC分类号： H04L7/0334

5. 发明专利

JP3840377B2 Saving circuit and method for driving an active matrix display 有权
公开(公告)号：JP3840377B2
公开(公告)日：2006-11-01
申请号：JP2000509014
申请日：1998-09-04
申请人：シリコン・イメージ,インコーポレーテッド
发明人：キム，ギュドン , キム，デオ−キョン
IPC分类号： G02F1/133 , G09G3/36 , G09G3/20
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3648 , G09G3/3688 , G09G2310/0248 , G09G2330/021 , G09G2330/023

6. 发明专利

JP2006500823A Detection and repair of Mpeg-2 chroma up-conversion artifacts 有权
公开(公告)号：JP2006500823A
公开(公告)日：2006-01-05
申请号：JP2004537974
申请日：2003-09-15
申请人：シリコン・イメージ,インコーポレーテッド
发明人：デールアダムス
IPC分类号： H04N7/26 , H04N5/44 , H04N9/64
CPC分类号： H04N9/646 , H04N7/012
摘要：【課題】必要とされているものは、ＭＰＥＧ−２画像の不正確なデコードによって起こされたビデオ画像の歪みを検出し、修理する方法とシステムである。
【解決手段】ビデオストリームの中でＭＰＥＧ−２彩度アップコンバートアーティファクトを取り除くための方法により、間違ってアップサンプリングされたＭＰＥＧ−２ビデオストリーム中のアーティファクトの存在の検出と、アーティファクトの除去とを含み、結果としてアーティファクトないビデオストリームとする。

7. 发明专利

JP3665536B2 Broadband delay locked loop circuit 有权
公开(公告)号：JP3665536B2
公开(公告)日：2005-06-29
申请号：JP2000157630
申请日：2000-05-29
申请人：シリコン・イメージ,インコーポレーテッド
发明人：ケオンギョ・リー , デオ−キョン・ジョン
IPC分类号： G06F1/10 , H03K5/13 , H03L7/00 , H03L7/08 , H03L7/081 , H03L7/087 , H03L7/089 , H03L7/10
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/0891 , H03L7/10 , H03L2207/14

9. 发明专利

JP5438616B2 Bidirectional data transmission using the video blanking interval of the digital data stream 有权
公开(公告)号：JP5438616B2
公开(公告)日：2014-03-12
申请号：JP2010165603
申请日：2010-07-23
申请人：シリコン・イメージ,インコーポレーテッド
发明人：マーティン，ラッセル，エイ
IPC分类号： G06F3/153 , H04N21/4363 , G09G5/00 , H04N7/083 , H04N7/084 , H04N7/085 , H04N7/087 , H04N7/088 , H04N21/4788
CPC分类号： G09G5/006 , G09G2370/04 , H04N7/083 , H04N11/042
摘要： Digital pixel data is transferred from a computer system to video display hardware in a forward direction. However, there are many reasons for digital pixel data to be transferred in both directions along a cable connecting a computer and a monitor. This invention describes a method of sending digital data from a monitor back to the computer in a reverse direction. In transmission of digital pixel data in a forward direction, there are horizontal and vertical blanking periods during which special characters are transmitted in order to resynchronize the digital pixel data to a clock signal. In such a system the transmission of these special characters only requires a portion of the blanking periods. During the remainder to the blanking period, some of or all of the data paths can be used in order to transmit digital data in a reverse direction. Where all data paths are used, the beginning and end of the usable portion of the blanking periods may last for a fixed number of clock cycles. Alternatively, the beginning and end of the usable portion of the blanking periods may be indicated by signals transmitted in a forward direction over one of the data paths, where all data paths are not used in a reverse direction.

10. 发明专利

JP4344475B2 cmos driver and the on-chip termination for data communication of gigabaud speed 有权
公开(公告)号：JP4344475B2
公开(公告)日：2009-10-14
申请号：JP2000540654
申请日：1999-01-20
申请人：シリコン・イメージ,インコーポレーテッド
发明人：アーン，ギジュン , キム，ギュドン , ジェオン，デオ−キョン
IPC分类号： H04L25/02 , H04L7/033
CPC分类号： H04L25/028 , H04L7/0337 , H04L25/0278 , H04L25/0292

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