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1. 发明授权

US6033975A Implant screen and method 失效
标题翻译：植入物屏和方法
公开(公告)号：US6033975A
公开(公告)日：2000-03-07
申请号：US992392
申请日：1997-12-17
申请人： Siang Ping Kwok , William F. Richardson , Dirk Noel Anderson , Jiann Liu
发明人： Siang Ping Kwok , William F. Richardson , Dirk Noel Anderson , Jiann Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/2652 , H01L29/66575
摘要： A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).
摘要翻译：半导体器件（60）可以包括具有外表面（20）的半导体层（12）。多个栅极（18）可以设置在半导体层（12）的外表面（20）上方。隔离罩（30）可以设置在门（18）之上。植入物筛（40）可以在栅极（18）的隔离盖（30）之间的半导体层（12）的外表面（20）上生长。

2. 发明授权

US06380008B2 Edge stress reduction by noncoincident layers 有权
标题翻译：非积层的边缘应力降低
公开(公告)号：US06380008B2
公开(公告)日：2002-04-30
申请号：US09738001
申请日：2000-12-14
申请人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
发明人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
IPC分类号： H01L2100
CPC分类号： H01L29/42376 , H01L21/28044 , H01L21/28114 , H01L29/4941
摘要： The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).
摘要翻译：薄膜导体边缘处的应力可以通过不重合的分层结构来减少，这样就可以利用边缘附近的拉伸到压缩特性应力极性，反之亦然，以避免器件的可靠性和性能问题。通过使用非重合分层结构，可以实现来自不同层的破坏性应力干扰，以减少边缘处的应力或应力梯度。本文公开的结构和方法可有利地用于许多集成电路和器件制造应用（包括门，字线和位线）中。

3. 发明授权

US06627938B2 Capacitor constructions 有权
标题翻译：电容器结构
公开(公告)号：US06627938B2
公开(公告)日：2003-09-30
申请号：US09729130
申请日：2000-12-01
申请人： Siang Ping Kwok , William F. Richardson
发明人： Siang Ping Kwok , William F. Richardson
IPC分类号： H01L27108
CPC分类号： H01L28/87 , H01L27/10855 , H01L28/91
摘要： In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.
摘要翻译：一方面，本发明包括形成电容器的方法。质量在电气节点上形成。在质量体内形成一个开口。开口具有靠近节点的下部和在下部上方的上部。下部比上部宽。第一导电层形成在开口内并且沿着开口的周边。在形成第一导电层之后，将质量的一部分从开口的上部旁边除去，而质量的另一部分留在开口的下部。在第一导电层上形成电介质材料，并且在电介质材料上形成第二导电层。第二导电层通过电介质材料与第一导电层分离。在另一方面，本发明包括电容器结构。

4. 发明授权

US06373088B1 Edge stress reduction by noncoincident layers 失效
公开(公告)号：US06373088B1
公开(公告)日：2002-04-16
申请号：US09096012
申请日：1998-06-10
申请人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
发明人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
IPC分类号： H01L2100
摘要： The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

5. 发明授权

US06429087B1 Methods of forming capacitors 有权
公开(公告)号：US06429087B1
公开(公告)日：2002-08-06
申请号：US09386537
申请日：1999-08-30
申请人： Siang Ping Kwok , William F. Richardson
发明人： Siang Ping Kwok , William F. Richardson
IPC分类号： H01L2120
摘要： In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.

6. 发明授权

US08583891B1 Associating partitions in a computing device 有权
标题翻译：在计算设备中关联分区
公开(公告)号：US08583891B1
公开(公告)日：2013-11-12
申请号：US13189783
申请日：2011-07-25
申请人： Randall R. Spangler , William A. Drewry , William F. Richardson
发明人： Randall R. Spangler , William A. Drewry , William F. Richardson
IPC分类号： G06F12/02
CPC分类号： G06F9/4406
摘要： Methods and apparatus for associating partitions in a computing device are disclosed. An example method includes, loading an operating system (O/S) kernel partition (kernel partition) and identifying one or more root filesystem (rootfs) partitions that are compatible with the loaded kernel partition. In the example method, the one or more compatible rootfs partitions are identified by comparing a set of compatibility bits of the loaded kernel partition with respective sets of compatibility bits of a plurality of rootfs partitions of the computing device. The example method still further includes selecting a rootfs partition from the one or more identified compatible rootfs partitions and loading the selected rootfs partition.
摘要翻译：公开了用于在计算设备中关联分区的方法和装置。一个示例方法包括：加载操作系统（O / S）内核分区（内核分区）并识别与加载的内核分区兼容的一个或多个根文件系统（rootfs）分区。在示例性方法中，通过将加载的内核分区的一组兼容性比特与计算设备的多个rootfs分区的相应的相应组的集合进行比较来识别一个或多个兼容的rootfs分区。该示例方法还包括从一个或多个所识别的兼容的rootfs分区中选择一个rootfs分区并加载所选的rootfs分区。

7. 发明授权

US6083809A Oxide profile modification by reactant shunting 失效
标题翻译：通过反应物分流改性氧化物
公开(公告)号：US6083809A
公开(公告)日：2000-07-04
申请号：US942058
申请日：1997-10-01
申请人： William F. Richardson , Yin Hu
发明人： William F. Richardson , Yin Hu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.
摘要翻译：一种制造半导体器件的方法和该器件，其包括最初提供其上具有薄氧化物层的硅层和至少选择的含氧物质不可渗透的掩蔽材料的图案化层，并且具有设置在所述氧化物上的侧壁以提供掩模材料和氧化物层的暴露交叉点。然后在掩蔽材料的侧壁上形成含氧物质导电路径，延伸到暴露的交叉点，用于导电选择的含氧物质。在导电路径上形成不同于导电路径的材料的侧壁层。然后将含氧物质通过路径施加到暴露的交叉点，并且围绕掩模材料的厚氧化物同时或作为单独的步骤制造。掩模材料优选为氮化硅，该路径优选为氧化硅，并且侧壁层优选为氮化硅。

8. 发明授权

US5017977A Dual EPROM cells on trench walls with virtual ground buried bit lines 失效
标题翻译：沟槽壁上的双EPROM单元具有虚拟地埋地线
公开(公告)号：US5017977A
公开(公告)日：1991-05-21
申请号：US471019
申请日：1990-01-19
申请人： William F. Richardson
发明人： William F. Richardson
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface in the bottom of the trenches which extend from one end to the other of the memory array.
摘要翻译：本发明的一个实施例提供了一种EPROM阵列，其具有形成在形成在半导体衬底中的沟槽的侧壁上的浮置栅极场效应晶体管。与这些沟槽壁晶体管的制造同时，在沟槽的底部中的沟槽之间形成列线，其从存储器阵列的一端延伸到另一端。

9. 发明授权

US08832455B1 Verified boot path retry 有权
标题翻译：验证的引导路径重试
公开(公告)号：US08832455B1
公开(公告)日：2014-09-09
申请号：US13239303
申请日：2011-09-21
申请人： William A. Drewry , William F. Richardson , Randall R. Spangler
发明人： William A. Drewry , William F. Richardson , Randall R. Spangler
IPC分类号： G06F21/00
CPC分类号： G06F21/575
摘要： Configurations providing a non-zero threshold for verifying a root file system of an operating system stored on blocks of a boot storage are disclosed. In particular, the root file system is verified during a boot sequence for the operating system. For each block of the root file system of the boot storage, the subject technology verifies a respective block of the boot storage. A counter tracking a number of verification failures is incremented if the block fails verification. In some configurations, the subject technology determines whether the counter meets a predetermined non-zero threshold. If the counter meets the predetermined non-zero threshold, the root file system is marked as corrupted. A recovery mode for the operating system is then initiated. If the counter does not meet the predetermined non-zero threshold, the operating system is reset in order to verify the root file system during a subsequent boot sequence.
摘要翻译：公开了提供用于验证存储在引导存储器的块上的操作系统的根文件系统的非零阈值的配置。特别地，根文件系统在操作系统的引导顺序期间被验证。对于引导存储器的根文件系统的每个块，主题技术验证引导存储器的相应块。跟踪多个验证失败的计数器如果块验证失败，则会递增。在一些配置中，主题技术确定计数器是否满足预定的非零阈值。如果计数器满足预定的非零阈值，则根文件系统被标记为已损坏。然后启动操作系统的恢复模式。如果计数器不满足预定的非零阈值，则操作系统被重置以便在随后的引导序列期间验证根文件系统。

10. 发明授权

US06496352B2 Post-in-crown capacitor and method of manufacture 有权
标题翻译：后置电容器及其制造方法
公开(公告)号：US06496352B2
公开(公告)日：2002-12-17
申请号：US09335348
申请日：1999-06-17
申请人： Darius L. Crenshaw , William F. Richardson , Rick L. Wise
发明人： Darius L. Crenshaw , William F. Richardson , Rick L. Wise
IPC分类号： H01G4005
CPC分类号： H01L28/91 , H01L21/3212 , H01L28/84
摘要： A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).
摘要翻译：公开了一种后置电容器。冠状后电容器（60）包括联接到导电通路（20）的表冠（44）。柱（48）设置在表冠（44）内，并且从表冠（44）和柱（48）向外形成电容器绝缘层（50）。然后从电容器绝缘层（50）向外形成电容器板层（52）。

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