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1. 发明授权

US6033975A Implant screen and method 失效
标题翻译：植入物屏和方法
公开(公告)号：US6033975A
公开(公告)日：2000-03-07
申请号：US992392
申请日：1997-12-17
申请人： Siang Ping Kwok , William F. Richardson , Dirk Noel Anderson , Jiann Liu
发明人： Siang Ping Kwok , William F. Richardson , Dirk Noel Anderson , Jiann Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/2652 , H01L29/66575
摘要： A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).
摘要翻译：半导体器件（60）可以包括具有外表面（20）的半导体层（12）。多个栅极（18）可以设置在半导体层（12）的外表面（20）上方。隔离罩（30）可以设置在门（18）之上。植入物筛（40）可以在栅极（18）的隔离盖（30）之间的半导体层（12）的外表面（20）上生长。

2. 发明授权

US5548548A Pass transistor for a 256 megabit dram with negatively biased substrate 失效
标题翻译：传输晶体管为256兆字节与负偏置的基板
公开(公告)号：US5548548A
公开(公告)日：1996-08-20
申请号：US358647
申请日：1994-12-19
申请人： Amitava Chatterjee , Jiann Liu , Purnendu Mozumder , Mark S. Rodder , Ih-Chin Chen
发明人： Amitava Chatterjee , Jiann Liu , Purnendu Mozumder , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L29/78 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/10 , H01L29/423 , G11C11/401
CPC分类号： H01L27/10873 , G11C11/404 , H01L29/1087 , H01L29/42364 , H01L29/42376
摘要： A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.
摘要翻译：实现256 Mbit DRAM器件的传输晶体管的设计。栅极长度约为0.3μm的晶体管，约为85安培的毒素，其比0.25微米逻辑技术的DIFFERENCE 65 ANGSTROM毒is厚，V VL为3.75伏，Vsub为-1伏，砷 LDD和沟道区域中的硼浓度约为2.7x1017 / cm3，是256 Mbit DRAM器件的理想选择。

3. 发明授权

US6030861A Method for forming dual-gate CMOS for dynamic random access memory 失效
标题翻译：用于形成用于动态随机存取存储器的双栅极CMOS的方法
公开(公告)号：US6030861A
公开(公告)日：2000-02-29
申请号：US1051
申请日：1997-12-30
申请人： Jiann Liu
发明人： Jiann Liu
IPC分类号： C07H21/00 , H01L21/8238
CPC分类号： C07H21/00 , H01L21/823842
摘要： A method for forming a dual-gate transistor includes the step of forming a gate oxide layer (18) over two transistor regions provided by a P-tank (12) and an N-tank (14). This is followed by depositing a layer of in-situ doped poly (20) and then masking off a portion of the poly layer (20) overlying the P-tank (12). This is then followed by diffusion of P-type impurities into the portion of the poly layer (20) overlying the N-tank (14) associated with the P-channel transistor. This is a process required for forming a DRAM memory. Utilizing the same oxide mask (22), a threshold implant is formed into the N-type (14).
摘要翻译：形成双栅极晶体管的方法包括在由P型罐（12）和N型槽（14）提供的两个晶体管区域上形成栅极氧化物层（18）的步骤。然后沉积一层原位掺杂的聚（20），然后掩盖覆盖P型槽（12）的多层（20）的一部分。然后将P型杂质扩散到覆盖与P沟道晶体管相关联的N槽（14）上的多晶硅层（20）的部分中。这是形成DRAM存储器所需的处理。利用相同的氧化物掩模（22），将阈值注入形成为N型（14）。

4. 发明授权

US06476448B2 Front stage process of a fully depleted silicon-on-insulator device and a structure thereof 失效
标题翻译：完全耗尽的绝缘体上硅器件及其结构的前级工艺
公开(公告)号：US06476448B2
公开(公告)日：2002-11-05
申请号：US09759971
申请日：2001-01-12
申请人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
发明人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
IPC分类号： H01L27088
CPC分类号： H01L21/84 , H01L27/1203
摘要： The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.
摘要翻译：描述了完全耗尽的SOI器件的前期工艺及其结构。提供了在绝缘层上方具有绝缘层和晶体硅层的SOI衬底。在晶体硅层中形成隔离层并连接到绝缘层以限定第一类型的MOS有源区。在第一型MOS有源区外部的晶体硅层的上方形成外延抑制层。在第一型MOS有源区中的晶体硅层上方选择性地形成第二类掺杂的外延硅层。第二型掺杂外延层原位掺杂。选择性地在第二种掺杂的外延硅层之上形成未掺杂的外延硅层。然后去除外延抑制层。

5. 发明授权

US5671175A Capacitor over bitline DRAM cell 失效
标题翻译：电容器在位线DRAM单元上
公开(公告)号：US5671175A
公开(公告)日：1997-09-23
申请号：US670079
申请日：1996-06-26
申请人： Jiann Liu , Clarence W. Teng
发明人： Jiann Liu , Clarence W. Teng
IPC分类号： H01L27/108 , G11C11/24
CPC分类号： H01L27/10808 , Y10S257/908
摘要： A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).
摘要翻译：具有降低的位线电容的DRAM阵列（100）。 DRAM单元包括传输晶体管和存储电容器（150）。隔离结构（108）围绕DRAM单元。位线（140）使用第一多晶硅插头（112）连接到传输晶体管的源极/漏极区域（120b）。第二多晶硅插头（110）将存储电容器（150）连接到传输晶体管的另一个源极/漏极区域（120a和c）。两个多晶硅插头（110,112）延伸穿过层间电介质层（116）到通过晶体管的源极/漏极区域（120a-c）之一，但是两者都不延伸到隔离结构（108）上。如果需要，存储电容器（150）或位线（140）可能偏离源极/漏极区域（120a-c）。

6. 发明授权

US06509218B2 Front stage process of a fully depleted silicon-on-insulator device 失效
标题翻译：完全耗尽的绝缘体上硅器件的前级工艺
公开(公告)号：US06509218B2
公开(公告)日：2003-01-21
申请号：US10119975
申请日：2002-04-09
申请人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
发明人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L27/1203
摘要： The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.
摘要翻译：描述了完全耗尽的SOI器件的前期工艺及其结构。提供了在绝缘层上方具有绝缘层和晶体硅层的SOI衬底。在晶体硅层中形成隔离层并连接到绝缘层以限定第一类型的MOS有源区。在第一型MOS有源区外部的晶体硅层的上方形成外延抑制层。在第一型MOS有源区中的晶体硅层上方选择性地形成第二类掺杂的外延硅层。第二型掺杂外延层原位掺杂。选择性地在第二种掺杂的外延硅层之上形成未掺杂的外延硅层。然后去除外延抑制层。

7. 发明授权

US06323073B1 Method for forming doped regions on an SOI device 失效
标题翻译：在SOI器件上形成掺杂区的方法
公开(公告)号：US06323073B1
公开(公告)日：2001-11-27
申请号：US09764399
申请日：2001-01-19
申请人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
发明人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
IPC分类号： H01L21338
CPC分类号： H01L29/78696 , H01L29/66772
摘要： An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer so as to form an N-well or P-well doped region. Next, a thermal diffusion process is performed to drive dopants into a second region of the silicon layer so as to form a P-well or N-well doped region. Finally, an epitaxy layer, having a thickness of about 200 angstroms, is grown on the surface of the silicon layer by way of a molecular-beam epitaxy (MBE) growth process, a liquid-phase epitaxy (LPE) growth process, or a vapor-phase epitaxy (VPE) growth process.
摘要翻译： SOI层具有在电介质层上形成的电介质层和硅层。在硅层上形成浅沟槽隔离结构。 STI结构通过介电层。执行热扩散处理以将掺杂剂驱动到硅层的第一区域中，以便形成N阱或P阱掺杂区域。接下来，进行热扩散处理以将掺杂剂驱动到硅层的第二区域中，以便形成P阱或N阱掺杂区域。最后，通过分子束外延（MBE）生长工艺，液相外延（LPE）生长工艺或液相外延生长工艺（LPE）生长工艺，在硅层的表面上生长具有约200埃厚度的外延层气相外延（VPE）生长过程。

8. 发明授权

US6140705A Self-aligned contact through a conducting layer 失效
标题翻译：通过导电层自对准接触
公开(公告)号：US6140705A
公开(公告)日：2000-10-31
申请号：US367644
申请日：1995-01-03
申请人： Jiann Liu
发明人： Jiann Liu
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/108 , H01L23/48
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76838 , H01L21/76897 , H01L23/485 , H01L2924/0002
摘要： A contact hole (32) is formed through a conducting layer (28). The conducting layer (28) is then undercut (34 and 36). An insulating layer (40) is formed in the contact hole (32). A contact (42) is then formed within the contact hole (32).
摘要翻译：通过导电层（28）形成接触孔（32）。导电层（28）然后是底切（34和36）。绝缘层（40）形成在接触孔（32）中。然后在接触孔（32）内形成触点（42）。

9. 发明授权

US4818326A Processing apparatus 失效
标题翻译：处理装置
公开(公告)号：US4818326A
公开(公告)日：1989-04-04
申请号：US188139
申请日：1988-04-26
申请人： Jiann Liu , Cecil J. Davis , Lee M. Loewenstein
发明人： Jiann Liu , Cecil J. Davis , Lee M. Loewenstein
IPC分类号： H01L21/00 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L21/67109
摘要： A processing apparatus and method for providing a process module with a low pressure, low energy ion implanter and a remote microwave plasma generator and a source of thermal energy, which is adapted to receive wafers for processing in a low pressure carrier.
摘要翻译：一种用于向处理模块提供低压，低能量离子注入机和远程微波等离子体发生器和热能源的处理装置和方法，其适于接收用于在低压载体中处理的晶片。

10. 发明授权

US5956614A Process for forming a metal-silicide gate for dynamic random access memory 失效
标题翻译：用于形成用于动态随机存取存储器的金属硅化物栅的方法
公开(公告)号：US5956614A
公开(公告)日：1999-09-21
申请号：US989983
申请日：1997-12-12
申请人： Jiann Liu
发明人： Jiann Liu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/78 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/4933 , H01L29/7833
摘要： A process for forming a titanium disilicide conductive layer on the upper surface of a poly gate is implemented within a self-aligned contact process. In this process, the poly layer is first formed followed by sputtering thereon of a refractory metal layer such as titanium. This is then covered by a nitride or oxide capping layer (18). A gate electrode mesa is then formed which will then have a layer of oxide (26) deposited thereon by an LPCVD technique. The temperature of this oxide deposition is such that the refractory metal layer (16) will react with the underlying poly layer (14) to form a titanium disilicide layer (28). This requires the temperature to be in excess of 600.degree. C. for this step. Thereafter, the layer (26) will be utilized to form a sidewall spacer region.
摘要翻译：在多孔栅极的上表面上形成二硅化钛导电层的工艺在自对准接触工艺中实现。在该方法中，首先形成多层，然后在其上溅射诸如钛的难熔金属层。然后由氮化物或氧化物覆盖层（18）覆盖。然后形成栅电极台面，然后通过LPCVD技术具有沉积在其上的氧化物层（26）。这种氧化物沉积的温度使得难熔金属层（16）将与下面的多层（14）反应以形成二硅化钛层（28）。这个步骤要求温度超过600℃。此后，层（26）将用于形成侧壁间隔区域。

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