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1. 发明申请

US20140061842A1 Multiple Metal Film Stack in BSI Chips 有权
标题翻译： BSI芯片中的多金属薄膜叠层
公开(公告)号：US20140061842A1
公开(公告)日：2014-03-06
申请号：US13604380
申请日：2012-09-05
申请人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
发明人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/1464 , H01L21/76838 , H01L27/14623 , H01L27/14687
摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
摘要翻译：一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。在第一导电层上形成第二导电层并与第一导电层接触。执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。执行第二图案化步骤以去除第一导电层的第一部分的一部分。在第二图案化步骤之后，第一导电层的第二和第三部分保留。

2. 发明授权

US08796805B2 Multiple metal film stack in BSI chips 有权
标题翻译： BSI芯片中的多个金属膜堆叠
公开(公告)号：US08796805B2
公开(公告)日：2014-08-05
申请号：US13604380
申请日：2012-09-05
申请人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
发明人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
IPC分类号： H01L31/00 , H01L21/00 , H01L27/146 , H01L21/768
CPC分类号： H01L27/1464 , H01L21/76838 , H01L27/14623 , H01L27/14687
摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
摘要翻译：一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。在第一导电层上形成第二导电层并与第一导电层接触。执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。执行第二图案化步骤以去除第一导电层的第一部分的一部分。在第二图案化步骤之后，第一导电层的第二和第三部分保留。

3. 发明授权

US09059057B2 Image sensor having compressive layers 有权
标题翻译：具有压缩层的图像传感器
公开(公告)号：US09059057B2
公开(公告)日：2015-06-16
申请号：US13492258
申请日：2012-06-08
申请人： Chun-Han Tsao , Chih-Yu Lai , Chih-Hui Huang , Cheng-Ta Wu , Yeur-Luen Tu , Ching-Chun Wang , Shyh-Fann Ting , Chia-Shiung Tsai
发明人： Chun-Han Tsao , Chih-Yu Lai , Chih-Hui Huang , Cheng-Ta Wu , Yeur-Luen Tu , Ching-Chun Wang , Shyh-Fann Ting , Chia-Shiung Tsai
IPC分类号： H01L31/102 , H01L21/00 , H01L27/146 , H01L27/148
CPC分类号： H01L31/02164 , H01L27/14623 , H01L27/14632 , H01L27/1464 , H01L27/14643 , H01L27/14687 , H01L27/148 , H01L51/4273
摘要： An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.
摘要翻译：一种包括具有阵列区域和黑色电平校正区域的半导体衬底的图像传感器装置。阵列区域包含多个辐射敏感像素。黑色电平校正区域包含一个或多个参考像素。基板具有前侧和后侧。图像传感器装置包括形成在基板的背面上的第一压缩应力层。第一压应力层含有氧化硅，带负电荷。第二压应力层含有氮化硅，带负电荷。在黑色电平校正区域的至少一部分上形成金属屏蔽。图像传感器装置包括形成在金属屏蔽和第二压缩应力层上的第三压缩应力层。第三压缩应力层含有氧化硅。金属屏蔽层的侧壁由第三压应力层保护。

4. 发明申请

US20130341746A1 Porous Si As CMOS Image Sensor ARC Layer 有权
标题翻译：多孔Si作为CMOS图像传感器ARC层
公开(公告)号：US20130341746A1
公开(公告)日：2013-12-26
申请号：US13556932
申请日：2012-07-24
申请人： Shyh-Fann Ting , Yen-Ting Chiang , Ching-Chun Wang
发明人： Shyh-Fann Ting , Yen-Ting Chiang , Ching-Chun Wang
IPC分类号： H01L31/0216 , H01L31/18
CPC分类号： H01L27/1464 , H01L27/14687
摘要： A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
摘要翻译：提供半导体器件。半导体器件包括由衬底支撑的金属化层，设置在金属化层上的二极管和部分掺杂的硅层，设置在二极管和部分掺杂硅层上的缓冲层; 以及设置在缓冲层上的抗反射涂层，由多孔硅形成的抗反射涂层。

5. 发明授权

US08686527B2 Porous Si as CMOS image sensor ARC layer 有权
标题翻译：多孔Si作为CMOS图像传感器ARC层
公开(公告)号：US08686527B2
公开(公告)日：2014-04-01
申请号：US13556932
申请日：2012-07-24
申请人： Shyh-Fann Ting , Yen-Ting Chiang , Ching-Chun Wang
发明人： Shyh-Fann Ting , Yen-Ting Chiang , Ching-Chun Wang
IPC分类号： H01L31/0232
CPC分类号： H01L27/1464 , H01L27/14687
摘要： A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
摘要翻译：提供半导体器件。半导体器件包括由衬底支撑的金属化层，设置在金属化层上的二极管和部分掺杂的硅层，设置在二极管和部分掺杂硅层上的缓冲层; 以及设置在缓冲层上的抗反射涂层，由多孔硅形成的抗反射涂层。

6. 发明申请

US20120199890A1 TRANSISTOR STRUCTURE 有权
标题翻译：晶体管结构
公开(公告)号：US20120199890A1
公开(公告)日：2012-08-09
申请号：US13450444
申请日：2012-04-18
申请人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L29/78
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.
摘要翻译：在本发明中提供一种晶体管结构。晶体管结构包括：包括P型阱的衬底，设置在P型阱上的栅极，设置在栅极上的第一间隔物，设置在栅极两侧的衬底中的N型源极/漏极区域覆盖N型源极/漏极区域的硅覆盖层，围绕第一间隔物的第二间隔物和第二间隔物，直接覆盖硅覆盖层的一部分并且覆盖硅覆盖层上的硅化物层。

7. 发明授权

US07928512B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07928512B2
公开(公告)日：2011-04-19
申请号：US11776562
申请日：2007-07-12
申请人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Chia-Wen Lang
发明人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Chia-Wen Lang
IPC分类号： H01L27/12
CPC分类号： H01L21/823412 , H01L21/823468 , H01L29/7842
摘要： A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.
摘要翻译：本文提供了一种半导体器件，其包括具有第一型MOS晶体管，形成在其上的输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管的衬底。半导体器件还包括第一应力层和第二应力层。第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。第二应力层设置在芯型二次型MOS晶体管上。

8. 发明申请

US20090137089A1 SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US20090137089A1
公开(公告)日：2009-05-28
申请号：US12366625
申请日：2009-02-05
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

9. 发明申请

US20080206942A1 METHOD FOR FABRICATING STRAINED-SILICON METAL-OXIDE SEMICONDUCTOR TRANSISTORS 有权
标题翻译：用于制备应变硅金属氧化物半导体晶体管的方法
公开(公告)号：US20080206942A1
公开(公告)日：2008-08-28
申请号：US11678627
申请日：2007-02-26
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Li-Shian Jeng , Kun-Hsien Lee , Wen-Han Hung , Tzyy-Ming Cheng , Meng-Yi Wu , Tsai-Fu Hsiao , Shu-Yen Chan
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Li-Shian Jeng , Kun-Hsien Lee , Wen-Han Hung , Tzyy-Ming Cheng , Meng-Yi Wu , Tsai-Fu Hsiao , Shu-Yen Chan
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.
摘要翻译：公开了制造应变硅晶体管的方法。首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

10. 发明授权

US07342284B2 Semiconductor MOS transistor device and method for making the same 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US07342284B2
公开(公告)日：2008-03-11
申请号：US11307660
申请日：2006-02-16
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

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