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1. 发明申请

US20140061842A1 Multiple Metal Film Stack in BSI Chips 有权
标题翻译： BSI芯片中的多金属薄膜叠层
公开(公告)号：US20140061842A1
公开(公告)日：2014-03-06
申请号：US13604380
申请日：2012-09-05
申请人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
发明人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/1464 , H01L21/76838 , H01L27/14623 , H01L27/14687
摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
摘要翻译：一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。在第一导电层上形成第二导电层并与第一导电层接触。执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。执行第二图案化步骤以去除第一导电层的第一部分的一部分。在第二图案化步骤之后，第一导电层的第二和第三部分保留。

2. 发明授权

US08796805B2 Multiple metal film stack in BSI chips 有权
标题翻译： BSI芯片中的多个金属膜堆叠
公开(公告)号：US08796805B2
公开(公告)日：2014-08-05
申请号：US13604380
申请日：2012-09-05
申请人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
发明人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
IPC分类号： H01L31/00 , H01L21/00 , H01L27/146 , H01L21/768
CPC分类号： H01L27/1464 , H01L21/76838 , H01L27/14623 , H01L27/14687
摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
摘要翻译：一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。在第一导电层上形成第二导电层并与第一导电层接触。执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。执行第二图案化步骤以去除第一导电层的第一部分的一部分。在第二图案化步骤之后，第一导电层的第二和第三部分保留。

3. 发明申请

US20140061738A1 Method to Form a CMOS Image Sensor 有权
标题翻译：形成CMOS图像传感器的方法
公开(公告)号：US20140061738A1
公开(公告)日：2014-03-06
申请号：US13602494
申请日：2012-09-04
申请人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Jiech-Fun Lu , Chun-Wei Chang , Wang-Pen Mo , Jhy-Jyi Sze , Chia-Shiung Tsai
发明人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Jiech-Fun Lu , Chun-Wei Chang , Wang-Pen Mo , Jhy-Jyi Sze , Chia-Shiung Tsai
IPC分类号： H01L31/0216
CPC分类号： H01L21/266 , H01L27/14689
摘要： The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.
摘要翻译：本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层，面具。形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。

4. 发明授权

US08759225B2 Method to form a CMOS image sensor 有权
标题翻译：形成CMOS图像传感器的方法
公开(公告)号：US08759225B2
公开(公告)日：2014-06-24
申请号：US13602494
申请日：2012-09-04
申请人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Jiech-Fun Lu , Chun-Wei Chang , Wang-Pen Mo , Jhy-Jyi Sze , Chia-Shiung Tsai
发明人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Jiech-Fun Lu , Chun-Wei Chang , Wang-Pen Mo , Jhy-Jyi Sze , Chia-Shiung Tsai
IPC分类号： H01L21/311
CPC分类号： H01L21/266 , H01L27/14689
摘要： The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.
摘要翻译：本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层，面具。形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。

5. 发明授权

US08278122B2 Method for forming MTJ cells 有权
标题翻译：形成MTJ细胞的方法
公开(公告)号：US08278122B2
公开(公告)日：2012-10-02
申请号：US12696771
申请日：2010-01-29
申请人： Jiech-Fun Lu , Shih-Chang Liu , Chia-Shiung Tsai
发明人： Jiech-Fun Lu , Shih-Chang Liu , Chia-Shiung Tsai
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222
摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.
摘要翻译：形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带电介质层并连接到顶部电极。

6. 发明申请

US20110189796A1 Uniformity in the Performance of MTJ Cells 有权
标题翻译： MTJ细胞表现的均匀性
公开(公告)号：US20110189796A1
公开(公告)日：2011-08-04
申请号：US12696771
申请日：2010-01-29
申请人： Jiech-Fun Lu , Shih-Chang Liu , Chia-Shiung Tsai
发明人： Jiech-Fun Lu , Shih-Chang Liu , Chia-Shiung Tsai
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , H01L27/222
摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.
摘要翻译：形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带电介质层并连接到顶部电极。

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