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1. 发明授权

US08758253B2 Ultrasonic probe and ultrasonic diagnostic apparatus using the same 有权
标题翻译：超声波探头和超声波诊断仪使用相同
公开(公告)号：US08758253B2
公开(公告)日：2014-06-24
申请号：US12513858
申请日：2007-11-06
申请人： Shuzo Sano , Akifumi Sako , Takashi Kobayashi , Mikio Izumi
发明人： Shuzo Sano , Akifumi Sako , Takashi Kobayashi , Mikio Izumi
IPC分类号： A61B8/14 , A61B8/00
CPC分类号： A61B8/4281 , A61B8/4455 , A61B8/4483 , B06B1/0292 , H04R19/005
摘要： An ultrasonic probe is disclosed which includes a cMUT chip having a plurality of vibration elements whose electromechanical coupling coefficient or sensitivity is changed according to a bias voltage and transmitting and receiving ultrasonic waves, an acoustic lens arranged above the cMUT chip, and a backing layer arranged below the cMUT chip. An electric leakage preventing unit is provided at the ultrasonic wave transmission/reception surface side of the acoustic lens or between the acoustic lens and the cMUT chip. The electric leakage preventing unit can be, for example, an insulating layer such as a ground layer. Such a structure makes it is possible to provide an ultrasonic probe capable of preventing electric leakage from the ultrasonic probe to an object to be examined so as to improve the electric safety and an ultrasonic diagnostic apparatus using the probe.
摘要翻译：公开了一种超声波探头，其包括具有多个振动元件的cMUT芯片，其中机电耦合系数或灵敏度根据偏置电压而变化，并且发送和接收超声波，布置在cMUT芯片上方的声透镜，以及布置在在cMUT芯片之下。在声透镜的超声波发送/接收表面侧或声透镜和cMUT芯片之间设置漏电防止单元。防漏电单元可以是例如绝缘层，例如接地层。通过这样的结构，能够提供能够防止从超声波探头向被检体的漏电以提高电气安全性的超声波探头以及使用该探针的超声波诊断装置。

2. 发明授权

US08540640B2 Ultrasonic probe and method for manufacturing the same and ultrasonic diagnostic device 有权
标题翻译：超声波探头及其制造方法及超声波诊断装置
公开(公告)号：US08540640B2
公开(公告)日：2013-09-24
申请号：US12525353
申请日：2008-02-27
申请人： Shuzo Sano , Akifumi Sako , Takashi Kobayashi , Mikio Izumi
发明人： Shuzo Sano , Akifumi Sako , Takashi Kobayashi , Mikio Izumi
IPC分类号： A61B8/14
CPC分类号： G01N29/2406 , B06B1/0292 , G01N29/0654 , G01N29/221 , G01N2291/106
摘要： An ultrasonic probe (2) comprises a cMUT chip (20), which has a plurality of vibration elements whose electromechanical coupling coefficient or the sensitivity changes depending on a bias voltage, and transmits/receives an ultrasonic wave; an acoustic lens (26) provided on the ultrasonic wave radiation side of the cMUT chip (20); a backing layer (22) provided on the back side of the cMUT chip (20) for absorbing propagation of the ultrasonic wave; an electric wiring portion (flexible substrate (72)), which is provided from the peripheral portion of the cMUT chip (20) to the side face of the backing layer (22) and has a signal pattern connected with the electrode of the cMUT chip (20) arranged thereon; and a housing (ultrasonic probe cover (25)) for containing the cMUT chip (20), the acoustic lens (26), the backing layer (22) and the electric wiring portion (flexible substrate (72)). A ground layer (conductive film (76)) of ground potential is provided on the ultrasonic wave radiation side of the cMUT chip (20).
摘要翻译：超声波探头（2）包括cMUT芯片（20），其具有多个振动元件，其机电耦合系数或灵敏度根据偏置电压而变化，并且发送/接收超声波; 设置在cMUT芯片（20）的超声波辐射侧的声透镜（26）; 设置在所述cMUT芯片（20）背面的用于吸收超声波传播的背衬层（22）; 从cMUT芯片（20）的周边部分到背衬层（22）的侧面设置的电连接部分（柔性基板（72）），并且具有与cMUT芯片的电极连接的信号图案（20）; 以及用于容纳cMUT芯片（20），声透镜（26），背层（22）和电布线部分（柔性基板（72））的外壳（超声波探头盖（25））。地电位的接地层（导电膜（76））设置在cMUT芯片（20）的超声波辐射侧。

3. 发明申请

US20100036257A1 ULTRASONIC PROBE AND ULTRASONIC DIAGNOSTIC APPARATUS USING THE SAME 有权
标题翻译：超声波探头和超声波诊断装置
公开(公告)号：US20100036257A1
公开(公告)日：2010-02-11
申请号：US12513858
申请日：2007-11-06
申请人： Shuzo Sano , Akifumi Sako , Takashi Kobayashi , Mikio Izumi
发明人： Shuzo Sano , Akifumi Sako , Takashi Kobayashi , Mikio Izumi
IPC分类号： A61B8/00
CPC分类号： A61B8/4281 , A61B8/4455 , A61B8/4483 , B06B1/0292 , H04R19/005
摘要： Provided is an ultrasonic probe including: a cMUT chip having a plurality of vibration elements whose electromechanical coupling coefficient or sensitivity is changed according to a bias voltage and transmitting and receiving ultrasonic waves; an acoustic lens arranged above the cMUT chip: and a backing layer arranged below the cMUT chip.Electric leakage preventing means is provided at the ultrasonic wave transmission/reception surface side of the acoustic lens or between the acoustic lens and the cMUT chip.The electric leakage preventing means is, for example, an insulating layer such as a ground layer.By using such a structure, it is possible to provide an ultrasonic probe capable of preventing electric leakage from the ultrasonic probe to an object to be examined so as to improve the electric safety and an ultrasonic diagnostic apparatus using the probe.
摘要翻译：本发明提供一种超声波探头，包括：cMUT芯片，具有多个振动元件，其机电耦合系数或灵敏度根据偏置电压而变化，并且发送和接收超声波; 布置在cMUT芯片上方的声透镜;以及布置在cMUT芯片下方的背衬层。在声透镜的超声波发射/接收表面侧或声透镜和cMUT芯片之间设置防漏电装置。漏电防止装置例如是诸如接地层的绝缘层。通过使用这样的结构，能够提供能够防止从超声波探头向被检体的电泄漏以提高电气安全性的超声波探头和使用该探针的超声波诊断装置。

4. 发明申请

US20100179430A1 ULTRASONIC PROBE AND METHOD FOR MANUFACTURING THE SAME AND ULTRASONIC DIAGNOSTIC DEVICE 有权
标题翻译：超声波探头及其制造方法及超声波诊断装置
公开(公告)号：US20100179430A1
公开(公告)日：2010-07-15
申请号：US12525353
申请日：2008-02-27
申请人： Shuzo Sano , Takashi Kobayashi , Mikio Izumi
发明人： Shuzo Sano , Takashi Kobayashi , Mikio Izumi
IPC分类号： A61B8/00 , H04R31/00
CPC分类号： G01N29/2406 , B06B1/0292 , G01N29/0654 , G01N29/221 , G01N2291/106
摘要： An ultrasonic probe (2) comprises a cMUT chip (20), which has a plurality of vibration elements whose electromechanical coupling coefficient or the sensitivity changes depending on a bias voltage, and transmits/receives an ultrasonic wave; an acoustic lens (26) provided on the ultrasonic wave radiation side of the cMUT chip (20); a backing layer (22) provided on the back side of the cMUT chip (20) for absorbing propagation of the ultrasonic wave; an electric wiring portion (flexible substrate (72)), which is provided from the peripheral portion of the cMUT chip (20) to the side face of the backing layer (22) and has a signal pattern connected with the electrode of the cMUT chip (20) arranged thereon; and a housing (ultrasonic probe cover (25)) for containing the cMUT chip (20), the acoustic lens (26), the backing layer (22) and the electric wiring portion (flexible substrate (72)). A ground layer (conductive film (76)) of ground potential is provided on the ultrasonic wave radiation side of the cMUT chip (20).
摘要翻译：超声波探头（2）包括cMUT芯片（20），其具有多个振动元件，其机电耦合系数或灵敏度根据偏置电压而变化，并且发送/接收超声波; 设置在cMUT芯片（20）的超声波辐射侧的声透镜（26）; 设置在所述cMUT芯片（20）背面的用于吸收超声波传播的背衬层（22）; 从cMUT芯片（20）的周边部分到背衬层（22）的侧面设置的电连接部分（柔性基板（72）），并且具有与cMUT芯片的电极连接的信号图案（20）; 以及用于容纳cMUT芯片（20），声透镜（26），背层（22）和电布线部分（柔性基板（72））的外壳（超声波探头盖（25））。地电位的接地层（导电膜（76））设置在cMUT芯片（20）的超声波辐射侧。

5. 发明授权

US10077485B2 Steel sheet for soft-nitriding and method for manufacturing the same 有权
公开(公告)号：US10077485B2
公开(公告)日：2018-09-18
申请号：US14409549
申请日：2012-06-27
申请人： Takashi Kobayashi , Nobuyuki Nakamura , Yoshimasa Funakawa
发明人： Takashi Kobayashi , Nobuyuki Nakamura , Yoshimasa Funakawa
IPC分类号： C22C38/26 , C21D6/00 , C22C38/00 , C22C38/06 , C22C38/04 , C21D9/46 , C21D8/02 , C22C38/02 , C22C38/24 , C22C38/38 , C23C8/26
CPC分类号： C21D9/46 , C21D6/002 , C21D6/005 , C21D6/008 , C21D8/0226 , C21D8/0263 , C21D2211/005 , C21D2211/009 , C22C38/00 , C22C38/001 , C22C38/02 , C22C38/04 , C22C38/06 , C22C38/24 , C22C38/26 , C22C38/38 , C23C8/26
摘要： A steel sheet for soft-nitriding has a composition containing: C: 0.05% or more to 0.10% or less; Si: 0.5% or less; Mn: 0.7% or more to 1.5% or less; P: 0.05% or less; S: 0.01% or less; Al: 0.01% or more to 0.06% or less; Cr: 0.5% or more to 1.5% or less; V: 0.03% or more to 0.30% or less; and N: 0.005% or less, on a mass percent basis, wherein a ratio of amount of solute V to the V content (amount of solute V/V content) is more than 0.50, and balance comprises Fe and incidental impurities, and a complex-phase microstructure containing ferrite and pearlite.

6. 发明申请

US20150299830A1 STEEL SHEET FOR SOFT-NITRIDING AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：用于软土的钢板及其制造方法
公开(公告)号：US20150299830A1
公开(公告)日：2015-10-22
申请号：US14408662
申请日：2012-06-27
申请人： Takashi Kobayashi , Nobuyuki Nakamura , Tetsuya Mega
发明人： Takashi Kobayashi , Nobuyuki Nakamura , Tetsuya Mega
IPC分类号： C22C38/26 , C21D9/46 , C22C38/00 , C22C38/06 , C22C38/04 , C22C38/02 , C21D8/02 , C21D6/00
CPC分类号： C22C38/26 , C21D6/002 , C21D6/005 , C21D6/008 , C21D8/0263 , C21D9/46 , C21D2211/005 , C21D2211/009 , C22C38/00 , C22C38/001 , C22C38/002 , C22C38/02 , C22C38/04 , C22C38/06 , C23C8/32
摘要： A steel sheet for soft-nitriding has a composition containing: C: 0.05% or more to 0.10% or less; Si: 0.5% or less; Mn: 0.7% or more to 1.5% or less; P: 0.05% or less; S: 0.01% or less; Al: 0.01% or more to 0.06% or less; Cr: 0.5% or more to 1.5% or less; Nb: 0.005% or more to 0.025% or less; and N: 0.005% or less, on a mass percent basis, such that C and Nb satisfy 0.10≦Nb/C≦0.30 (where C and Nb are respective contents of the elements (by mass %)), wherein balance comprises Fe and incidental impurities, and a microstructure that is a complex-phase microstructure containing ferrite and pearlite, and the microstructure having a ratio of a microstructure other than the ferrite and the pearlite of 1% or less, and the microstructure having a ratio of polygonal ferrite in the ferrite of less than 50%.
摘要翻译：软氮化钢板的组成为：C：0.05％以上且0.10％以下， Si：0.5％以下; Mn：0.7％以上至1.5％以下; P：0.05％以下; S：0.01％以下; Al：0.01％以上至0.06％以下; Cr：0.5％以上至1.5％以下; Nb：0.005％以上至0.025％以下; 和N：0.005％以下，C和Nb满足0.10＆nlE; Nb / C＆lt; NlE; 0.30（其中，C和Nb分别为元素含量（质量％）），其中余量包含Fe 和杂质，以及包含铁素体和珠光体的复相组织的显微组织以及具有1％以下的铁素体和珠光体以外的组织比的微结构，以及具有多边形铁素体在铁素体中小于50％。

7. 发明授权

US08866123B2 Non-volatile memory device and production method thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08866123B2
公开(公告)日：2014-10-21
申请号：US13884331
申请日：2010-11-22
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Takahiro Morikawa , Akio Shima , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Takahiro Morikawa , Akio Shima , Takashi Kobayashi
IPC分类号： H01L47/00 , H01L45/00 , H01L29/792 , H01L27/24 , H01L29/66 , H01L27/115
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
摘要翻译：垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接双层选择晶体管。利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

8. 发明授权

US08835872B2 Sample stage device 有权
标题翻译：样品台装置
公开(公告)号：US08835872B2
公开(公告)日：2014-09-16
申请号：US13806989
申请日：2011-06-23
申请人： Takashi Kobayashi
发明人： Takashi Kobayashi
IPC分类号： H01J37/20
CPC分类号： H01J37/20 , H01J2237/20285 , H01J2237/20292 , H01J2237/2817 , H01L21/68
摘要： A sample stage device (10) is so configured as to calculate ideal position information xtg(i), tg(i) per predetermined period that is unaffected by drive conditions relating to gaps (25, 26), etc., and to determine, per predetermined cycle and in real time, deviations dx(i), dy(i) between real-time measured positions x(i), y(i) by position detectors comprising laser interferometers (33, 34), etc., and ideal position information xtg(i), tg(i). In addition, it calculates, based on deviations dx(i), dy(i) thus determined, such speed command values vx(i), vy(i) for motors (27, 28) that measured values x(i), y(i) would follow ideal position information xtg(i), tg(i), and performs stable and high-speed positioning control for a sample table (11) through feedback control that controls speed in real time. Thus, with respect to a sample stage device, it is possible to provide a stable and high-speed positioning control method for a sample table, which is capable of suppressing noise caused by thermal drift and vibration, without being affected by drive conditions, such as the initial states of gaps, etc.
摘要翻译：样品台装置（10）被配置为计算不受与间隙（25,26）等有关的驱动条件的影响的每预定周期的理想位置信息xtg（i），tg（i）并且实时地通过包括激光干涉仪（33,34）的位置检测器等实时测量位置x（i），y（i）之间的偏差dx（i），dy（i）和理想位置信息xtg（i），tg（i）。另外，根据如此确定的偏差dx（i），dy（i），计算出测量值x（i），y（i）的电动机（27,28）的速度指令值vx（i），vy （i）将遵循理想位置信息xtg（i），tg（i），并且通过实时控制速度的反馈控制对样本表（11）执行稳定和高速定位控制。因此，对于样品台装置，可以提供一种用于样品台的稳定且高速的定位控制方法，其能够抑制由热漂移和振动引起的噪声，而不受驱动条件的影响，例如作为差距的初始状态等

9. 发明授权

US08772746B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08772746B2
公开(公告)日：2014-07-08
申请号：US13349653
申请日：2012-01-13
申请人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi
发明人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2454 , H01L27/2472 , H01L45/144 , H01L45/1675
摘要： A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.
摘要翻译：可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。在半导体存储器件中，连续地沿着Y方向延伸的多个字线形成栅极绝缘膜，沿X方向延伸的沟道和沿X方向延伸的电阻变化元件，并且沟道的一部分和电阻变化元件的一部分设置在多条字线的上方。这样的配置可以减小单元面积并确保设计自由度。

10. 发明授权

US08642988B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08642988B2
公开(公告)日：2014-02-04
申请号：US13588112
申请日：2012-08-17
申请人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi , Hiroyuki Minemura
发明人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi , Hiroyuki Minemura
IPC分类号： H01L29/02
CPC分类号： H01L45/144 , G11C13/0004 , G11C2213/71 , G11C2213/74 , G11C2213/75 , G11C2213/78 , H01L27/2409 , H01L27/2481 , H01L45/06
摘要： A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.
摘要翻译：非易失性存储器件包括：沿衬底的主表面延伸的第一线; 提供在第一行之上的堆栈; 在堆叠之上形成第二线; 设置在所述第一和第二线相交的选择元件，所述选择元件适于在垂直于所述主表面的方向上传递电流; 沿着所述堆叠的侧表面设置的第二绝缘膜; 沿所述第二绝缘膜设置的沟道层; 沿着沟道层提供的粘合层; 以及沿着粘合层设置的可变电阻材料层，其中第一和第二线经由选择元件和沟道层电连接，通过沟道层和可变电阻材料层之间的粘合层的接触电阻低，并且粘合层的电阻相对于沟道层的延伸方向高。

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