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    • 6. 发明申请
    • SHIFT REGISTER AND SEMICONDUCTOR DISPLAY DEVICE
    • SHIFT寄存器和半导体显示器件
    • US20120019300A1
    • 2012-01-26
    • US13248420
    • 2011-09-29
    • Mitsuaki OSAMEAya ANZAI
    • Mitsuaki OSAMEAya ANZAI
    • H03K3/356
    • G09G3/3677G09G3/3266G09G3/3275G09G3/3688G11C19/00G11C19/28
    • The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.
    • 本发明提供了一种能够在抑制信号延迟和波形舍入的同时正常工作的移位寄存器。 本发明的移位寄存器包括多个级的触发器电路,每个触发器电路包括时钟反相器。 时钟反相器包括串联连接的第一晶体管和第二晶体管,包括串联连接的第三晶体管和第四晶体管的第一补偿电路和包括第五晶体管和透射栅的第二补偿电路。 根据第一补偿电路,可以与前两级的输出同步地控制从触发器电路输出的信号上升或下降的定时。 第二补偿电路可以控制时钟信号输入可以控制。
    • 7. 发明申请
    • CLOCKED INVERTER, NAND, NOR AND SHIFT REGISTER
    • 时钟逆变器,NAND,NOR和移位寄存器
    • US20090201077A1
    • 2009-08-13
    • US12427103
    • 2009-04-21
    • Mitsuaki OSAMEAya ANZAI
    • Mitsuaki OSAMEAya ANZAI
    • G05F1/10
    • H03K19/018521G11C19/00G11C19/28H03K19/00384H03K19/0963
    • A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series. In the clocked inverter, gates of the third transistor and the fourth transistor are connected to each other, drains of the third transistor and the fourth transistor are each connected to a gate of the first transistor, sources of the first transistor and the fourth transistor are each electrically connected to a first power source, a source of the second transistor is electrically connected to a second power source, and an amplitude of a signal inputted to a source of the third transistor is smaller than a potential difference between the first power source and the second power source.
    • 晶体管的阈值电压由于栅极绝缘膜的膜厚的波动或由于使用的衬底的差异或制造步骤引起的栅极长度和栅极宽度而波动。 为了解决该问题,根据本发明,提供了一种包括串联连接的第一晶体管和第二晶体管的时钟反相器,以及包括串联连接的第三晶体管和第四晶体管的补偿电路。 在时钟反相器中,第三晶体管和第四晶体管的栅极彼此连接,第三晶体管和第四晶体管的漏极分别连接到第一晶体管的栅极,第一晶体管和第四晶体管的源极 每个电连接到第一电源,第二晶体管的源极电连接到第二电源,并且输入到第三晶体管的源极的信号的幅度小于第一电源和第二电源之间的电位差, 第二个电源。
    • 8. 发明申请
    • SHIFT REGISTER AND SEMICONDUCTOR DISPLAY DEVICE
    • SHIFT寄存器和半导体显示器件
    • US20110068824A1
    • 2011-03-24
    • US12953038
    • 2010-11-23
    • Mitsuaki OSAMEAya ANZAI
    • Mitsuaki OSAMEAya ANZAI
    • H03K19/173G05F1/10
    • G09G3/3677G09G3/3266G09G3/3275G09G3/3688G11C19/00G11C19/28
    • The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.
    • 本发明提供了一种能够在抑制信号延迟和波形舍入的同时正常工作的移位寄存器。 本发明的移位寄存器包括多个级的触发器电路,每个触发器电路包括时钟反相器。 时钟反相器包括串联连接的第一晶体管和第二晶体管,包括串联连接的第三晶体管和第四晶体管的第一补偿电路和包括第五晶体管和透射栅的第二补偿电路。 根据第一补偿电路,可以与前两级的输出同步地控制从触发器电路输出的信号上升或下降的定时。 第二补偿电路可以控制时钟信号输入可以控制。