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1. 发明授权

US08222686B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08222686B2
公开(公告)日：2012-07-17
申请号：US13097731
申请日：2011-04-29
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. A manufacturing technique for a semiconductor device including a nonvolatile memory cell having control gate and memory gate electrodes is also featured.
摘要翻译：一种具有非易失性存储单元的半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的控制电极，用作控制栅电极的栅极绝缘体的第一绝缘膜，形成在所述半导体衬底上的第二绝缘膜，以及形成在所述第二绝缘膜上并与所述控制栅电极相邻的存储栅电极，所述第二绝缘膜用作所述存储栅电极的栅极绝缘体，并且具有非导电电荷所述控制栅电极具有与所述存储栅电极不同的导电类型。还提出了一种包括具有控制栅极和存储栅电极的非易失性存储单元的半导体器件的制造技术。

2. 发明申请

US20120112265A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120112265A1
公开(公告)日：2012-05-10
申请号：US13350703
申请日：2012-01-13
申请人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

3. 发明申请

US20100149875A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100149875A1
公开(公告)日：2010-06-17
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

4. 发明申请

US20090090961A1 Non-Volatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090090961A1
公开(公告)日：2009-04-09
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

5. 发明授权

US07166893B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07166893B2
公开(公告)日：2007-01-23
申请号：US10252101
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

6. 发明授权

US07119406B2 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
公开(公告)号：US07119406B2
公开(公告)日：2006-10-10
申请号：US11178375
申请日：2005-07-12
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

7. 发明申请

US20060205130A1 Semiconductor integrated circuit device and its manufacturing method 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060205130A1
公开(公告)日：2006-09-14
申请号：US11401839
申请日：2006-04-12
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/8234 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7926
摘要： A semiconductor integrated circuit device has a plurality of rows of pillars, each row being composed of semiconductor pillars and insulator pillars alternately arranged in one direction with no gap therebetween, a plurality of nonvolatile memory elements provided individually in said plurality of semiconductor pillars, said plurality of nonvolatile memory elements having control gate electrodes provided over side surfaces of said semiconductor pillars along said one direction via gate insulating films, drain regions provided in upper surface portions of said semiconductor pillars, and source regions provided in bottom surface portions of said semiconductor pillars, and lines including the respective control gate electrodes of said plurality of nonvolatile memory elements and provided along said one direction over the side surfaces of said rows of pillars along said one direction.
摘要翻译：半导体集成电路器件具有多排支柱，每行由半导体柱和绝缘体柱组成，所述半导体柱和绝缘体柱在一个方向上交替排列，没有间隙，多个非易失性存储元件分别设置在所述多个半导体柱中，所述多个具有通过栅极绝缘膜沿着所述一个方向设置在所述半导体柱的侧表面上的控制栅极的非易失性存储元件，设置在所述半导体柱的上表面部分中的漏极区域和设置在所述半导体柱的底表面部分中的源极区域，以及包括所述多个非易失性存储元件的各个控制栅极的线，并且沿着所述一个方向沿着所述一排柱的侧表面沿所述一个方向设置。

8. 发明申请

US20060140004A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060140004A1
公开(公告)日：2006-06-29
申请号：US11360590
申请日：2006-02-24
申请人： Shoji Shukuri , Kazumasa Yanagisawa
发明人： Shoji Shukuri , Kazumasa Yanagisawa
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0441 , G11C2216/10
摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.
摘要翻译：半导体集成电路包括非易失性存储元件（PM 1，PM 2），每一个都具有第一源电极，第一漏电极，浮栅电极和控制栅极，并且能够具有不同的阈值电压，并读取晶体管元件（DM1，DM2），每个晶体管元件具有第二源极和第二漏极，并且能够根据非易失性存储元件的阈值电压具有不同的互导。读取晶体管元件具有根据电子注入状态或电子发射状态的切换状态，换句话说，浮置栅电极的写入状态或擦除状态。在读取操作中，不需要根据非易失性存储元件的阈值电压使通道电流流动。

9. 发明申请

US20060138568A1 Semiconductor integrated circuit device and a methodof manufacturing the same 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060138568A1
公开(公告)日：2006-06-29
申请号：US11359291
申请日：2006-02-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L29/76
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

10. 发明授权

US07067373B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
公开(公告)号：US07067373B2
公开(公告)日：2006-06-27
申请号：US10767069
申请日：2004-01-30
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor integrated circuit device capable of reading memory information from an on-chipped nonvolatile memory cell transistor at high speed. The memory cell transistor includes, in a first well region, a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between the pair of memory electrodes, and includes, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of a reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

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