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1. 发明申请

US20060140004A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060140004A1
公开(公告)日：2006-06-29
申请号：US11360590
申请日：2006-02-24
申请人： Shoji Shukuri , Kazumasa Yanagisawa
发明人： Shoji Shukuri , Kazumasa Yanagisawa
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0441 , G11C2216/10
摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.
摘要翻译：半导体集成电路包括非易失性存储元件（PM 1，PM 2），每一个都具有第一源电极，第一漏电极，浮栅电极和控制栅极，并且能够具有不同的阈值电压，并读取晶体管元件（DM1，DM2），每个晶体管元件具有第二源极和第二漏极，并且能够根据非易失性存储元件的阈值电压具有不同的互导。读取晶体管元件具有根据电子注入状态或电子发射状态的切换状态，换句话说，浮置栅电极的写入状态或擦除状态。在读取操作中，不需要根据非易失性存储元件的阈值电压使通道电流流动。

2. 发明授权

US06791881B2 Semiconductor device 失效
公开(公告)号：US06791881B2
公开(公告)日：2004-09-14
申请号：US10627821
申请日：2003-07-28
申请人： Shoji Shukuri , Kazumasa Yanagisawa
发明人： Shoji Shukuri , Kazumasa Yanagisawa
IPC分类号： H01L2710
CPC分类号： G11C16/26 , G11C16/0441 , G11C2216/10
摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.

3. 发明授权

US07405971B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07405971B2
公开(公告)日：2008-07-29
申请号：US11360590
申请日：2006-02-24
申请人： Shoji Shukuri , Kazumasa Yanagisawa
发明人： Shoji Shukuri , Kazumasa Yanagisawa
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0441 , G11C2216/10
摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.
摘要翻译：半导体集成电路包括非易失性存储元件（PM 1，PM 2），每一个都具有第一源电极，第一漏电极，浮栅电极和控制栅极，并且能够具有不同的阈值电压，并读取晶体管元件（DM1，DM2），每个晶体管元件具有第二源极和第二漏极，并且能够根据非易失性存储元件的阈值电压具有不同的互导。读取晶体管元件具有根据电子注入状态或电子发射状态的切换状态，换句话说，浮置栅电极的写入状态或擦除状态。在读取操作中，不需要根据非易失性存储元件的阈值电压使通道电流流动。

4. 发明申请

US20050152186A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20050152186A1
公开(公告)日：2005-07-14
申请号：US11072309
申请日：2005-03-07
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.

5. 发明授权

US06628549B2 Semiconductor device 失效
公开(公告)号：US06628549B2
公开(公告)日：2003-09-30
申请号：US10230314
申请日：2002-08-29
申请人： Shoji Shukuri , Kazumasa Yanagisawa
发明人： Shoji Shukuri , Kazumasa Yanagisawa
IPC分类号： G11C700
CPC分类号： G11C16/26 , G11C16/0441 , G11C2216/10
摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.

6. 发明授权

US06611458B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06611458B2
公开(公告)日：2003-08-26
申请号：US09780393
申请日：2001-02-12
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C1606
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件，通过第一层多晶硅或非易失性存储元件在对半导体集成电路进行测试时被编程，从而在形成非易失性存储元件时不需要特殊工艺，也就是说，可以在形成CMOS器件和器件的过程中形成非易失性存储元件用于编程的激光束不需要，因为在测试中进行编程，可以缩短编程所需的时间，因此可以降低测试成本。

7. 发明授权

US06466482B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06466482B2
公开(公告)日：2002-10-15
申请号：US09801769
申请日：2001-03-09
申请人： Shoji Shukuri , Kazumasa Yanagisawa
发明人： Shoji Shukuri , Kazumasa Yanagisawa
IPC分类号： G11C700
CPC分类号： G11C16/26 , G11C16/0441 , G11C2216/10
摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.
摘要翻译：半导体集成电路包括非易失性存储元件（PM1，PM2），其中每一个具有第一源电极，第一漏电极，浮栅电极和控制栅电极，并且能够具有不同的阈值电压，并读取晶体管元件（DM1，DM2），每个晶体管元件具有第二源极和第二漏极，并且能够根据非易失性存储元件的阈值电压具有不同的互导。读取晶体管元件具有根据电子注入状态或电子发射状态的切换状态，换句话说，浮置栅电极的写入状态或擦除状态。在读取操作中，不需要根据非易失性存储元件的阈值电压使通道电流流动。

8. 发明授权

US07149113B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07149113B2
公开(公告)日：2006-12-12
申请号：US11072309
申请日：2005-03-07
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮动电极的非易失性存储元件，通过第一（第二）存储来存储半导体中存储单元阵列的缺陷的地址多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。结果，在形成非易失性存储元件中不需要特殊的处理。换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。因此，可以缩短编程所需的时间，因此可以降低测试成本。

9. 发明授权

US06894944B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06894944B2
公开(公告)日：2005-05-17
申请号：US10602684
申请日：2003-06-25
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮动电极的非易失性存储元件，通过第一（第二）存储来存储半导体中存储单元阵列的缺陷的地址多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。结果，在形成非易失性存储元件中不需要特殊的处理。换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。因此，可以缩短编程所需的时间，因此可以降低测试成本。

10. 发明授权

US08829968B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08829968B2
公开(公告)日：2014-09-09
申请号：US12555143
申请日：2009-09-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO1〜MIO4）通常用于连接电路块。

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