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1. 发明授权

US06559895B1 Analog memory and image processing system for reducing fixed pattern noise 有权
标题翻译：用于减少固定模式噪声的模拟记忆和图像处理系统
公开(公告)号：US06559895B1
公开(公告)日：2003-05-06
申请号：US09508447
申请日：2000-03-10
申请人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
发明人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
IPC分类号： H04N978
CPC分类号： G11C27/04 , G11C27/024
摘要： Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic. In this manner, charge feed through noise of the respective storage elements (21) are made substantially uniform, resulting in suppressing the fixed pattern noise.
摘要翻译：模拟存储器的固定模式噪声降低。在地址产生单元（10）和用于存储模拟信号的各个存储元件（21）之间的地址选择信号（SL）的传输路径被构造为在通过地址驱动存储元件（21）时具有基本均匀的电特性选择信号（SL）使得模拟存储器的输出信号没有固定模式噪声的程度。用于临时存储和输出地址选择信号的缓冲单元（50）设置在地址生成单元（10）和各个存储元件（21）之间，缓冲单元（50）被构造成具有基本均匀的输出特性在所述存储元件（21）之间。此外，缓冲单元（50）和存储元件（21）之间的线被构造成具有基本上相同的电特性。以这种方式，通过各个存储元件（21）的噪声的电荷馈送被制成基本均匀，导致抑制固定图案噪声。

2. 发明授权

US06121826A Comb filter and method for controlling the same 失效
标题翻译：梳状滤波器及其控制方法
公开(公告)号：US06121826A
公开(公告)日：2000-09-19
申请号：US210780
申请日：1998-12-15
申请人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
发明人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
IPC分类号： H04N9/78 , H03K5/00
CPC分类号： H04N9/78
摘要： A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal. Accordingly, a large-capacitance capacitor, which has been required for stabilizing the control signal, is no longer necessary.
摘要翻译：提供了一种梳状滤波器，可以在不使用大容量电容器的情况下容易地实现为单片LSI。梳状频率特性由用于延迟相互不同时间量的信号的两个延迟电路和用于导出其输出的和或差的运算电路实现。在图像信号的消隐间隔期间，输入选择开关选择性地输出作为具有预定幅度的DC信号的测试信号而不是图像信号。检测器根据测试信号和预定参考信号之间的梳状滤波器的输出信号之间的差异来控制提供给任一个延迟电路的输出的可变增益放大器的增益。也就是说，通过使用稳定的测试信号作为控制信号来控制梳状滤波器的增益，而不是包含在不稳定图像信号中的突发信号。因此，不再需要用于稳定控制信号所需的大容量电容器。

3. 发明授权

US06552402B1 Composite MOS transistor device 有权
标题翻译：复合MOS晶体管器件
公开(公告)号：US06552402B1
公开(公告)日：2003-04-22
申请号：US09287310
申请日：1999-04-07
申请人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
发明人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
IPC分类号： H01L2976
CPC分类号： H01L21/823456 , H01L27/088
摘要： A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated. Accordingly, in forming a differential amplifier or a current mirror circuit using this MOS transistor pair, high current gain can be obtained while maintaining an adequate balance in output current.
摘要翻译：用于半导体集成电路的复合MOS晶体管器件至少包括一对放置在同一板上的MOS晶体管或第一和第二MOS晶体管。第一和第二MOS晶体管分别由具有相等栅极宽度的等分分割晶体管组成。这些分离的晶体管在栅极纵向方向上彼此平行地布置。这些组的分割晶体管被布置成使得从中心线测量的各个栅极的坐标之和在栅极纵向方向上在这些组之间相等。由于各组栅极沿其长度的误差之和在每组分割晶体管中变为零，所以可以消除两个MOS晶体管之间的电流差。因此，在形成使用该MOS晶体管对的差分放大器或电流镜电路时，可以在保持输出电流的充分平衡的同时获得高电流增益。

4. 发明授权

US06215162B1 Composite MOS transistor device 有权
公开(公告)号：US06215162B1
公开(公告)日：2001-04-10
申请号：US09287310
申请日：1999-04-07
申请人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
发明人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
IPC分类号： H01L2976
摘要： A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated. Accordingly, in forming a differential amplifier or a current mirror circuit using this MOS transistor pair, high current gain can be obtained while maintaining an adequate balance in output current.

5. 发明申请

US20090153203A1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：US20090153203A1
公开(公告)日：2009-06-18
申请号：US12066000
申请日：2006-07-27
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

6. 发明授权

US4985319A Process for manufacturing a photomask 失效
标题翻译：光掩模制造工艺
公开(公告)号：US4985319A
公开(公告)日：1991-01-15
申请号：US425088
申请日：1989-10-23
申请人： Yaichiro Watakabe , Tatsuo Okamoto , Shuichi Matsuda
发明人： Yaichiro Watakabe , Tatsuo Okamoto , Shuichi Matsuda
IPC分类号： G03F1/00 , G03F1/54 , H01L21/027
CPC分类号： G03F1/54
摘要： A photomask manufacturing process including a step of forming metal silicide film on a transparent silica glass substrate. A resist is applied onto the metal silicide film and then a patterning mask is provided by light or electron beam, followed by developing step. Exposed portions of the metal silicide film is etched away using a dry etching process.

7. 发明授权

US4903117A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4903117A
公开(公告)日：1990-02-20
申请号：US203445
申请日：1988-06-07
申请人： Tatsuo Okamoto , Ikuo Ogoh
发明人： Tatsuo Okamoto , Ikuo Ogoh
IPC分类号： H01L29/43 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/41
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： A silicon oxide film and a BPSG film are formed on a silicon substrate to serve as insulating films, and a contact hole is selectively formed in the insulating films. An impurity diffusion layer is formed on the surface layer of the semiconductor substrate at the bottom portion of the contact hole. A second metal film serving as a metal electrode is formed to cover the BPSG film and the impurity diffusion layer, and a first metal film serving as a barrier layer is formed between the second metal film and the BPSG film and impurity diffusion layer. The first metal film prevents boron contained in the BPSG film from being diffused in the second metal film, thereby to prevent precipitation of silicon in the contact hole.
摘要翻译：在硅衬底上形成氧化硅膜和BPSG膜以用作绝缘膜，并且在绝缘膜中选择性地形成接触孔。在接触孔的底部的半导体衬底的表面层上形成杂质扩散层。形成用作金属电极的第二金属膜以覆盖BPSG膜和杂质扩散层，并且在第二金属膜和BPSG膜和杂质扩散层之间形成用作阻挡层的第一金属膜。第一金属膜防止BPSG膜中含有的硼扩散到第二金属膜中，从而防止硅在接触孔中析出。

8. 发明授权

US4872050A Interconnection structure in semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件的互连结构及其制造方法
公开(公告)号：US4872050A
公开(公告)日：1989-10-03
申请号：US168386
申请日：1988-03-15
申请人： Tatsuo Okamoto , Hideo Kotani , Takio Oono , Kiyoto Watabe , Yasushi Kinoshita , Yoshikazu Nishikawa
发明人： Tatsuo Okamoto , Hideo Kotani , Takio Oono , Kiyoto Watabe , Yasushi Kinoshita , Yoshikazu Nishikawa
IPC分类号： H01L23/485 , H01L23/522
CPC分类号： H01L24/02 , H01L21/76805 , H01L23/5226 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/014 , H01L2924/05042
摘要： Conductive layers (5a, 9a) included in a multi-layer structure (30a) are electrically interconnected through a conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) exisitng under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).
摘要翻译：包含在多层结构（30a）中的导电层（5a，9a）通过设置在接触孔（12）中并与多层结构（30a）的侧表面（22）接触的导电连接壁（30a）。存在于层叠结构体（30a）的多层结构（30a）和下导电层（3）上的上导电层（11a）通过设置在接触孔中的导电膜（11b）电连接（12）。这两个互连通过设置在连接壁（13a）上的绝缘膜（18）彼此绝缘。

9. 发明授权

US4043037A Cord-type mowing tool 失效
标题翻译：线式割草工具
公开(公告)号：US4043037A
公开(公告)日：1977-08-23
申请号：US732588
申请日：1976-10-14
申请人： Tatsuo Okamoto , Masat Nogawa , Nobuyoshi Okabe
发明人： Tatsuo Okamoto , Masat Nogawa , Nobuyoshi Okabe
IPC分类号： A01D34/73 , A01D34/416 , A01D55/18 , B27B27/00
CPC分类号： A01D34/416
摘要： A cord-type mowing tool having a cutter body formed with at least one radially extending bore for receiving a cord serving as a grass cutting blade, and a clamping member fitted in the central bottom opening of the cutter body for forcing against the central portion of the cutter body an end portion of the cord inserted in the radially extending bore to hold the cord in place. The clamping member is threadably connected to the cutter body, so that by loosening and tightening the threadable connection it is possible to readily replace the old cord by a new cord of a predetermined length. The grass cutting tool is simple in construction, light in weight and reliable in performance.
摘要翻译：一种绳型割草工具，其具有形成有至少一个径向延伸的孔的刀体，用于接收用作草切刀的绳索，以及夹紧构件，其装配在刀体的中心底部开口中，用于迫使其抵抗切割器主体将插入径向延伸的孔中的绳索的端部保持在适当的位置。夹紧构件螺纹连接到切割器主体，从而通过松开和拧紧可螺纹连接，可以用预定长度的新的线容易地更换旧的绳索。草切工具施工简单，重量轻，性能可靠。

10. 发明申请

US20110115531A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20110115531A1
公开(公告)日：2011-05-19
申请号：US13014362
申请日：2011-01-26
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/095 , H03B19/00 , H03L7/10
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

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