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1. 发明授权

US06643730B2 CPU controlled memory controlling device for accessing operational information 失效
标题翻译：用于访问操作信息的CPU控制存储器控制装置
公开(公告)号：US06643730B2
公开(公告)日：2003-11-04
申请号：US09879118
申请日：2001-06-13
申请人： Yoshiki Okumura , Yoshihiro Takamatsuya , Tomohiro Hayashi , Shinkichi Gama , Takeshi Nagase
发明人： Yoshiki Okumura , Yoshihiro Takamatsuya , Tomohiro Hayashi , Shinkichi Gama , Takeshi Nagase
IPC分类号： G06F1200
CPC分类号： G06F12/06
摘要： A memory controlling device is controlled by a CPU to enable information to be read from memory when the memory starts an operation. The memory is capable of retaining data during a power off state and the data is loaded when the memory starts an operation.
摘要翻译：存储器控制装置由CPU控制，以便当存储器开始操作时使得能够从存储器读取信息。存储器能够在断电状态期间保留数据，并且当存储器开始操作时数据被加载。

2. 发明授权

US06339809B1 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers 有权
公开(公告)号：US06339809B1
公开(公告)日：2002-01-15
申请号：US09281232
申请日：1999-03-30
申请人： Shinkichi Gama , Takeshi Nagase , Yoshiki Okumura , Tomohiro Hayashi , Yoshihiro Takamatsuya
发明人： Shinkichi Gama , Takeshi Nagase , Yoshiki Okumura , Tomohiro Hayashi , Yoshihiro Takamatsuya
IPC分类号： G06F1200
CPC分类号： G11C8/04 , G06F5/00 , G11C8/06
摘要： A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.

3. 发明授权

US06289411B1 Circuit for generating a chip-enable signal for a multiple chip configuration 失效
标题翻译：用于产生用于多芯片配置的芯片使能信号的电路
公开(公告)号：US06289411B1
公开(公告)日：2001-09-11
申请号：US09282195
申请日：1999-03-31
申请人： Yoshiki Okumura , Yoshihiro Takamatsuya , Tomohiro Hayashi , Shinkichi Gama , Takeshi Nagase
发明人： Yoshiki Okumura , Yoshihiro Takamatsuya , Tomohiro Hayashi , Shinkichi Gama , Takeshi Nagase
IPC分类号： G06F1200
CPC分类号： G06F12/06
摘要： A circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.
摘要翻译：一种可用于能够具有m个芯片的第一设备和具有多于m个芯片的第二设备的芯片的电路包括：第一生成单元，其生成包括m位的位模式以使能的芯片使能信号由芯片号码表示的m个芯片中的一个，第二代单元，其生成待解码为至少2m位的芯片使能信号的芯片使能生成信号，以使得能够使用由所述芯片编号，所述芯片使能产生信号包括当所述芯片数等于特定数量时与m位的位模式相同的位模式;以及选择单元，其选择并输出由所述第一模块生成的所述芯片使能信号当电路用于第一装置时，生成单元，并且当电路用于第二装置时，选择并输出由第二代单元产生的芯片使能生成信号。

4. 发明授权

US06449681B1 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers 失效
标题翻译：存储单元和缓冲器访问控制电路，用于在连续访问上缓冲区和下缓冲区时更新地址
公开(公告)号：US06449681B1
公开(公告)日：2002-09-10
申请号：US09989109
申请日：2001-11-21
申请人： Shinkichi Gama , Takeshi Nagase , Yoshiki Okumura , Tomohiro Hayashi , Yoshihiro Takamatsuya
发明人： Shinkichi Gama , Takeshi Nagase , Yoshiki Okumura , Tomohiro Hayashi , Yoshihiro Takamatsuya
IPC分类号： G06F1200
CPC分类号： G11C8/04 , G06F5/00 , G11C8/06
摘要： A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.
摘要翻译：一个缓冲器访问控制电路，用于访问分配有相同地址的上缓冲器和下缓冲器的缓冲器以及包括缓冲存取控制电路的存储单元。缓冲器访问控制电路包括响应于上缓冲器访问信号和下缓冲存取信号而存储数据的锁存电路，以及检测由锁存电路锁存的数据是否匹配的第一检测电路。当生成上部和下部缓冲器访问信号之一并且检测电路检测到匹配时，修改电路将数据输入到第一和第二锁存器或将反相数据输入到第一和第二锁存器。以这种方式，缓冲器访问控制电路用于逐个更新地址，而在连续访问上下缓冲器时不使用延迟电路。

5. 发明授权

US06418501B1 Memory card 有权
标题翻译：存储卡
公开(公告)号：US06418501B1
公开(公告)日：2002-07-09
申请号：US09280708
申请日：1999-03-30
申请人： Shinkichi Gama , Yoshiki Okumura , Takeshi Nagase , Tomohiro Hayashi , Yoshihiro Takamatsuya
发明人： Shinkichi Gama , Yoshiki Okumura , Takeshi Nagase , Tomohiro Hayashi , Yoshihiro Takamatsuya
IPC分类号： G06F1300
CPC分类号： G06F13/4086
摘要： A memory card realizes two interface standards. The memory card includes an input terminal receiving a grounded or open-circuited signal from a host unit when using the memory card in conformance with a first interface standard, and receiving a binary signal from the host unit when using the memory card in conformance with a second interface standard, a first circuit acquiring standard information which indicates the first or second interface standard, from a signal issued from the host unit, a second circuit outputting a high-level voltage when using the memory card in conformance with the first interface standard and outputting a high-impedance signal when using the memory card in conformance with the second interface standard, depending on the standard information acquired by the first circuit, and a resistor coupling an output of the second circuit and the input terminal.
摘要翻译：存储卡实现两个接口标准。存储卡包括输入端，当使用符合第一接口标准的存储卡时，从主机单元接收接地或开路信号，并且当使用符合第一接口标准的存储卡时从主机单元接收二进制信号第二接口标准，从主机单元发出的信号中获取指示第一或第二接口标准的标准信息的第一电路，当使用符合第一接口标准的存储卡时输出高电平电压的第二电路;以及根据由第一电路获取的标准信息，以及耦合第二电路的输出和输入端的电阻器，在按照第二接口标准使用存储卡时输出高阻抗信号。

6. 发明授权

US08143901B2 Test apparatus, test method, and integrated circuit 失效
标题翻译：测试仪器，测试方法和集成电路
公开(公告)号：US08143901B2
公开(公告)日：2012-03-27
申请号：US12379371
申请日：2009-02-19
申请人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
发明人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
IPC分类号： G01R31/02
CPC分类号： G11C29/20 , G11C29/56004 , G11C2029/3602
摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
摘要翻译：测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

7. 发明授权

US07689836B2 Encryption device 有权
标题翻译：加密设备
公开(公告)号：US07689836B2
公开(公告)日：2010-03-30
申请号：US11312611
申请日：2005-12-21
申请人： Takeshi Nagase , Shogo Shibazaki , Shinkichi Gama
发明人： Takeshi Nagase , Shogo Shibazaki , Shinkichi Gama
IPC分类号： H04L9/32 , H04L9/00
CPC分类号： G06F21/85 , G06F21/602 , G06F21/78
摘要： An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.
摘要翻译：加密/解密处理单元执行从主机系统发送的数据的加密/解密处理以及用于数据的加密/解密的密钥数据的加密/解密处理。密钥数据缓冲器临时存储加密的密钥数据。密钥数据缓冲区临时存储未加密的密钥数据。外部存储器接口控制外部附加的闪存，并读取/写入存储在密钥数据缓冲器中的加密密钥数据。

8. 发明申请

US20090296505A1 Memory test method and memory test device 有权
标题翻译：内存测试方法和内存测试设备
公开(公告)号：US20090296505A1
公开(公告)日：2009-12-03
申请号：US12382485
申请日：2009-03-17
申请人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
发明人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
摘要翻译：通过顺序地生成多个n位地址来执行存储器测试，其中第一至第k位（1 <= k <= n）都被设置为两个值0或1之一，并且其（k + 对于从1到n的所有k，所有1到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

9. 发明授权

US08503259B2 Memory test method and memory test device 有权
标题翻译：内存测试方法和内存测试设备
公开(公告)号：US08503259B2
公开(公告)日：2013-08-06
申请号：US12382485
申请日：2009-03-17
申请人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
发明人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
摘要翻译：通过顺序地生成多个n位地址来执行存储器测试，其中第一到第k位（1 @ k @ n）都被设置为两个值0或1中的一个，并且其（k + 1）对于从1到n的所有k，所有第th到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

10. 发明申请

US20090300443A1 Test apparatus, test method, and integrated circuit 失效
标题翻译：测试仪器，测试方法和集成电路
公开(公告)号：US20090300443A1
公开(公告)日：2009-12-03
申请号：US12379371
申请日：2009-02-19
申请人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
发明人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
IPC分类号： G06F11/22
CPC分类号： G11C29/20 , G11C29/56004 , G11C2029/3602
摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
摘要翻译：测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

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