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1. 发明授权

US5648975A Method and device for generating test patterns for testing integrated circuit 失效
标题翻译：用于产生测试集成电路测试模式的方法和装置
公开(公告)号：US5648975A
公开(公告)日：1997-07-15
申请号：US595508
申请日：1996-02-01
申请人： Chikahiro Deguchi
发明人： Chikahiro Deguchi
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3181
CPC分类号： G01R31/318371
摘要： A method and apparatus for selecting test patterns of a plurality of groups of test patterns for testing parts of an integrated circuit. The plurality of groups of test patterns are applied to the parts of the integrated circuit to determine which parts are detected by the plurality of groups of test patterns. The detected parts form a group of parts. Each of the groups of test patterns is selectively identified as either necessary or unnecessary by repeatedly referring to the group of parts. Each time a respective group of test patterns is determined to be necessary, the group of parts is reduced by the parts detected by the respective group of test patterns determined to be necessary. After each of the groups of test patterns has been identified as either necessary or unnecessary, the unnecessary groups of test patterns are eliminated, to form a set of remaining necessary groups of test patterns for testing the integrated circuit.
摘要翻译：一种用于选择用于测试集成电路的部件的多组测试图案的测试图案的方法和装置。将多组测试图案应用于集成电路的各部分，以确定由多组测试图案检测哪些部件。检测到的零件形成一组零件。通过重复地引用该组零件，将每组测试图案选择性地识别为必需或不必要的。每当确定相应组的测试模式是必要的时，该组的部件被确定为必要的各组测试模式检测到的部分减少。在将每组测试图案确定为必需或不必要的组之后，消除不必要的测试图案组，以形成用于测试集成电路的一组剩余的测试图案组。

2. 发明授权

US08503259B2 Memory test method and memory test device 有权
标题翻译：内存测试方法和内存测试设备
公开(公告)号：US08503259B2
公开(公告)日：2013-08-06
申请号：US12382485
申请日：2009-03-17
申请人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
发明人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
摘要翻译：通过顺序地生成多个n位地址来执行存储器测试，其中第一到第k位（1 @ k @ n）都被设置为两个值0或1中的一个，并且其（k + 1）对于从1到n的所有k，所有第th到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

3. 发明申请

US20090296505A1 Memory test method and memory test device 有权
标题翻译：内存测试方法和内存测试设备
公开(公告)号：US20090296505A1
公开(公告)日：2009-12-03
申请号：US12382485
申请日：2009-03-17
申请人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
发明人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
摘要翻译：通过顺序地生成多个n位地址来执行存储器测试，其中第一至第k位（1 <= k <= n）都被设置为两个值0或1之一，并且其（k + 对于从1到n的所有k，所有1到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

4. 发明授权

US07158638B2 Encryption circuit 有权
标题翻译：加密电路
公开(公告)号：US07158638B2
公开(公告)日：2007-01-02
申请号：US10034321
申请日：2002-01-03
申请人： Souichi Okada , Naoya Torii , Tomohiro Hayashi , Chikahiro Deguchi , Yumi Fujiwara
发明人： Souichi Okada , Naoya Torii , Tomohiro Hayashi , Chikahiro Deguchi , Yumi Fujiwara
IPC分类号： H04K1/04
CPC分类号： H04L9/0631 , H04L2209/122 , H04L2209/24
摘要： An encryption circuit that reduces a scale of circuit and can achieve a certain level of high-speed processing in the implementation of the AES block cipher. A round processing unit comprises: a first Round Key Addition circuit that adds a round key value to input data; an intermediate register/Shift Row transformation circuit that temporarily stores the output of the first Round Key Addition circuit and executes Shift Row transformation; a Byte Sub transformation circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which executes Byte Sub transformation; a second Round Key Addition circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which adds round key values; a Mix Column transformation circuit that executes Mix Column transformation upon the outputs of the second Round Key Addition circuit; and a second selector that outputs to the second Round Key Addition circuit one of the outputs of a first selector, the intermediate register/Shift Row transformation circuit, the Byte Sub transformation circuit, and the Mix Column transformation circuit.
摘要翻译：一种减少电路规模的加密电路，可在实现AES块密码时实现一定程度的高速处理。圆处理单元包括：向输入数据添加循环密钥值的第一循环密钥加法电路; 中间寄存器/移位行变换电路，暂时存储第一循环密钥加法电路的输出，并执行移位行变换; 输入中间寄存器/移位行变换电路的值并执行Byte Sub变换的字节子变换电路; 第二循环密钥加法电路，其中输入中间寄存器/移位行变换电路的值，并加上循环键值; 混合列变换电路，对第二循环密钥加法电路的输出执行混合列变换; 以及第二选择器，其向第二圆形加法电路输出第一选择器，中间寄存器/移位行变换电路，字节子变换电路和混合列变换电路的输出之一。

5. 发明授权

US08143901B2 Test apparatus, test method, and integrated circuit 失效
标题翻译：测试仪器，测试方法和集成电路
公开(公告)号：US08143901B2
公开(公告)日：2012-03-27
申请号：US12379371
申请日：2009-02-19
申请人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
发明人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
IPC分类号： G01R31/02
CPC分类号： G11C29/20 , G11C29/56004 , G11C2029/3602
摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
摘要翻译：测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

6. 发明授权

US08436644B2 Configuration method and FPGA circuit re-executing configuration based on adjusted configuration data 失效
标题翻译：基于调整配置数据的配置方法和FPGA电路重新执行配置
公开(公告)号：US08436644B2
公开(公告)日：2013-05-07
申请号：US13064236
申请日：2011-03-11
申请人： Hiroaki Watanabe , Naoki Maezawa , Chikahiro Deguchi
发明人： Hiroaki Watanabe , Naoki Maezawa , Chikahiro Deguchi
IPC分类号： H03K19/173
CPC分类号： H03K19/00 , H03K19/17764 , H03K19/17776
摘要： A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.
摘要翻译：配置方法通过将配置数据从配置电路设置到FPGA电路来执行FPGA电路的配置。该方法在FPGA电路中计数了FPGA电路配置失败的次数。该方法在FPGA电路内调整配置数据，如果计数值超过上限值，则配置失败，并根据调整后的配置数据重新执行配置。当配置成功时，该方法将配置从FPGA电路成功配置到配置电路。

7. 发明申请

US20110227605A1 Configuration method and FPGA circuit 失效
标题翻译：配置方法和FPGA电路
公开(公告)号：US20110227605A1
公开(公告)日：2011-09-22
申请号：US13064236
申请日：2011-03-11
申请人： Hiroaki Watanabe , Naoki Maezawa , Chikahiro Deguchi
发明人： Hiroaki Watanabe , Naoki Maezawa , Chikahiro Deguchi
IPC分类号： H03K19/173
CPC分类号： H03K19/00 , H03K19/17764 , H03K19/17776
摘要： A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.
摘要翻译：配置方法通过将配置数据从配置电路设置到FPGA电路来执行FPGA电路的配置。该方法在FPGA电路中计数了FPGA电路配置失败的次数。该方法在FPGA电路内调整配置数据，如果计数值超过上限值，则配置失败，并根据调整后的配置数据重新执行配置。当配置成功时，该方法将配置成功从FPGA电路配置到配置电路。

8. 发明申请

US20090300443A1 Test apparatus, test method, and integrated circuit 失效
标题翻译：测试仪器，测试方法和集成电路
公开(公告)号：US20090300443A1
公开(公告)日：2009-12-03
申请号：US12379371
申请日：2009-02-19
申请人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
发明人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
IPC分类号： G06F11/22
CPC分类号： G11C29/20 , G11C29/56004 , G11C2029/3602
摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
摘要翻译：测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

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