会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明申请
    • Optical semiconductor device and method of manufacturing the same
    • 光半导体装置及其制造方法
    • US20070295977A1
    • 2007-12-27
    • US11896154
    • 2007-08-30
    • Shinichi HiroseTatsuya Usuki
    • Shinichi HiroseTatsuya Usuki
    • H01L33/00H01L21/00
    • H01S5/34B82Y10/00B82Y20/00H01L33/385H01S5/0425H01S5/3412Y10S438/962Y10S977/774Y10S977/932
    • Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including at least one quantum dot 23; a p-type contact layer (or a contact layer) 26 formed on top of the active layer 25 and being of an opposite conduction type to the n-type contact layer 21; an insulating layer 29 formed on top of the p-type contact layer 26 and including a first opening 29a whose size is such that a contact region CR of the p-type contact layer 26 lies within the first opening 29a; a p-side electrode layer 33c formed on top of the contact region CR of the p-type contact layer 26 and on top of the insulating layer 29 and including a second opening 33a lying within the first opening 29a; and a n-side electrode layer (or a second electrode layer) 37 formed on the other surface 20b of the GaAs substrate 20.
    • 提供了包括GaAs衬底(或半导体衬底)20的光学半导体器件; 形成在GaAs衬底20的一个表面上的n型接触层(或掺杂层)21; 形成在n型接触层21的顶部并且包括至少一个量子点23的有源层25; 形成在有源层25顶部并且与n型接触层21具有相反导电型的p型接触层(或接触层)26; 形成在p型接触层26的顶部上的绝缘层29,包括第一开口29a,第一开口29a的尺寸使得p型接触层26的接触区域CR位于第一开口29a内; p型电极层33c,其形成在p型接触层26的接触区域CR的顶部和绝缘层29的顶部上,并且包括位于第一开口部21a内的第二开口部33a; 以及形成在GaAs衬底20的另一个表面20b上的n侧电极层(或第二电极层)37。
    • 7. 发明授权
    • Optical semiconductor device and method of manufacturing the same
    • 光半导体装置及其制造方法
    • US07679076B2
    • 2010-03-16
    • US11896154
    • 2007-08-30
    • Shinichi HiroseTatsuya Usuki
    • Shinichi HiroseTatsuya Usuki
    • H01L29/06
    • H01S5/34B82Y10/00B82Y20/00H01L33/385H01S5/0425H01S5/3412Y10S438/962Y10S977/774Y10S977/932
    • Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including at least one quantum dot 23; a p-type contact layer (or a contact layer) 26 formed on top of the active layer 25 and being of an opposite conduction type to the n-type contact layer 21; an insulating layer 29 formed on top of the p-type contact layer 26 and including a first opening 29a whose size is such that a contact region CR of the p-type contact layer 26 lies within the first opening 29a; a p-side electrode layer 33c formed on top of the contact region CR of the p-type contact layer 26 and on top of the insulating layer 29 and including a second opening 33a lying within the first opening 29a; and a n-side electrode layer (or a second electrode layer) 37 formed on the other surface 20b of the GaAs substrate 20.
    • 提供了包括GaAs衬底(或半导体衬底)20的光学半导体器件; 形成在GaAs衬底20的一个表面20a上的n型接触层(或掺杂层)21; 形成在n型接触层21的顶部并且包括至少一个量子点23的有源层25; 形成在有源层25顶部并且与n型接触层21具有相反导电型的p型接触层(或接触层)26; 形成在p型接触层26的顶部的绝缘层29,其包括尺寸使得p型接触层26的接触区域CR位于第一开口29a内的第一开口29a; p型电极层33c,其形成在p型接触层26的接触区域CR的顶部和绝缘层29的顶部,并且包括位于第一开口29a内的第二开口33a; 以及形成在GaAs衬底20的另一个表面20b上的n侧电极层(或第二电极层)37。
    • 8. 发明授权
    • Direct tunneling semiconductor memory device and fabrication process thereof
    • 直接隧道半导体存储器件及其制造工艺
    • US07432153B2
    • 2008-10-07
    • US11898685
    • 2007-09-14
    • Kouji TsunodaTatsuya Usuki
    • Kouji TsunodaTatsuya Usuki
    • H01L21/336
    • H01L27/11521H01L27/115H01L29/42324H01L29/7883
    • A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.
    • 直接隧道半导体存储器件包括形成在半导体衬底上的器件隔离结构,包括器件隔离沟槽和填充器件隔离沟槽的器件隔离绝缘膜,覆盖两个侧壁表面的电介质膜和浮动栅极的顶表面 形成在所述半导体基板上的电极,经由所述电介质膜设置在所述浮栅电极的侧壁面上的导电部,构成控制栅电极的一部分的导体部,以及形成在所述第一扩散区 浮置栅电极,其中所述第一和第二扩散区形成在所述器件隔离槽的表面上,偏离所述浮置栅电极正下方的区域,所述导电部分形成在所述器件区域中,偏离所述器件隔离沟槽。
    • 10. 发明授权
    • Direct tunneling semiconductor memory device and fabrication process thereof
    • 直接隧道半导体存储器件及其制造工艺
    • US07288813B2
    • 2007-10-30
    • US11012277
    • 2004-12-16
    • Kouji TsunodaTatsuya Usuki
    • Kouji TsunodaTatsuya Usuki
    • H01L29/788
    • H01L27/11521H01L27/115H01L29/42324H01L29/7883
    • A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.
    • 直接隧道半导体存储器件包括形成在半导体衬底上的器件隔离结构,包括器件隔离沟槽和填充器件隔离沟槽的器件隔离绝缘膜,覆盖两个侧壁表面的电介质膜和浮动栅极的顶表面 形成在所述半导体基板上的电极,经由所述电介质膜设置在所述浮栅电极的侧壁面上的导电部,构成控制栅电极的一部分的导体部,以及形成在所述第一扩散区 浮置栅电极,其中所述第一和第二扩散区形成在所述器件隔离槽的表面上,偏离所述浮置栅电极正下方的区域,所述导电部分形成在所述器件区域中,偏离所述器件隔离沟槽。