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1. 发明申请

US20090086530A1 System and method for reading multiple magnetic tunnel junctions with a single select transistor 有权
公开(公告)号：US20090086530A1
公开(公告)日：2009-04-02
申请号：US11865481
申请日：2007-10-01
申请人： Shine Chung , Denny Tang , Fu-Lung Hsueh
发明人： Shine Chung , Denny Tang , Fu-Lung Hsueh
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2213/75 , G11C2213/78
摘要： A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.

2. 发明授权

US07577020B2 System and method for reading multiple magnetic tunnel junctions with a single select transistor 有权
标题翻译：用单个选择晶体管读取多个磁隧道结的系统和方法
公开(公告)号：US07577020B2
公开(公告)日：2009-08-18
申请号：US11865481
申请日：2007-10-01
申请人： Shine Chung , Denny Tang , Fu-Lung Hsueh
发明人： Shine Chung , Denny Tang , Fu-Lung Hsueh
IPC分类号： G11C11/00 , G11C11/15 , G11C15/00
CPC分类号： G11C13/003 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2213/75 , G11C2213/78
摘要： A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.
摘要翻译：一种用于读取与选择晶体管串联连接以形成存储器串的两个或多个磁隧道结（MTJ）的方法，所述方法包括接通选择晶体管，测量存储器串的第一电阻，存储第一电阻，切换MTJ中的预定的一个，在切换之后测量存储器串的第二电阻，反转预定的一个MTJ，并用多个预定电阻值比较第一和第二电阻，其中比较结果导致确定存储在MTJ中的数据。

3. 发明授权

US08258602B2 Bipolar junction transistors having a fin 有权
标题翻译：具有翅片的双极结晶体管
公开(公告)号：US08258602B2
公开(公告)日：2012-09-04
申请号：US12618425
申请日：2009-11-13
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/73 , H01L21/823431
摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.
摘要翻译：描述用于制造双极结型晶体管的设计和方法。在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。第二翅片邻近并平行于第一翅片设置。第二鳍片包括与第一基底区域的第一接触。

4. 发明授权

US08183910B2 Circuit and method for a digital process monitor 有权
标题翻译：数字过程监控的电路和方法
公开(公告)号：US08183910B2
公开(公告)日：2012-05-22
申请号：US12495024
申请日：2009-06-30
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G01R31/3004 , G01R31/31703
摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.
摘要翻译：公开了一种用于数字处理监视器的电路和方法。公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号。处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。使用数字滤波和数字信号处理等数字技术进行校准。数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。可以使用探针焊盘或扫描测试电路来访问过程监控电路。公开了使用数字输出来监视与过程有关的特性的方法。

5. 发明授权

US07663445B2 Voltage-control oscillator circuits with combined MOS and bipolar device 有权
标题翻译：具有组合MOS和双极器件的压控振荡器电路
公开(公告)号：US07663445B2
公开(公告)日：2010-02-16
申请号：US12237187
申请日：2008-09-24
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1212 , H03B5/1215 , H03B5/1231 , H03B5/124
摘要： A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.
摘要翻译：压控振荡器包括：具有第一双极晶体管和第一MOS晶体管的第一合并器件，所述第一双极晶体管具有与第一MOS晶体管的源极/漏极共用公共有效面积的集电极，以及共享公共具有第一MOS晶体管的另一源/漏极的有源区，具有第二双极晶体管和第二MOS晶体管的第二合并器件，所述第二双极晶体管具有与第二MOS晶体管的源极/漏极共用共用有效面积的集电极以及与第二MOS晶体管的另一个源极/漏极共用公共有源区域的发射极，以及连接到第一双极晶体管的集电极和第二双极晶体管的基极的第一电感器。

6. 发明授权

US07612638B2 Waveguides in integrated circuits 有权
标题翻译：集成电路中的波导
公开(公告)号：US07612638B2
公开(公告)日：2009-11-03
申请号：US11486903
申请日：2006-07-14
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01P3/00 , H01P3/12 , H01P3/14 , H01P1/00 , H01P1/06
CPC分类号： H01P3/12 , H01L2924/0002 , H01L2924/00
摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.
摘要翻译：公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。

7. 发明申请

US20090002058A1 Automatic Bias Circuit for Sense Amplifier 有权
标题翻译：用于检测放大器的自动偏置电路
公开(公告)号：US20090002058A1
公开(公告)日：2009-01-01
申请号：US11769611
申请日：2007-06-27
申请人： Po Yao Ker , Shine Chung , Fu-Lung Hsueh
发明人： Po Yao Ker , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01H37/76 , G11C5/14
CPC分类号： G11C17/18 , G11C5/147
摘要： The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.
摘要翻译：本发明公开了一种用于感测放大器的偏置电路，其具有被感测的器件，该感测器件处于非编程状态和编程状态，该偏置电路包括至少一个第一分支，该第一分支具有至少一个基本上形成与感测下的设备相同并且保持在未编程状态，并且至少一个第二设备形成也与感测下的设备基本相同并处于编程状态，其中至少一个第一设备和至少一个第二设备串联连接。本发明的典型应用是电熔丝存储器。

8. 发明授权

US08957482B2 Electrical fuse and related applications 有权
标题翻译：电熔丝及相关应用
公开(公告)号：US08957482B2
公开(公告)日：2015-02-17
申请号：US12731325
申请日：2010-03-25
申请人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
发明人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
IPC分类号： H01L23/62 , H01L27/06 , H01L23/525 , H01L27/112 , H01L27/10 , H01L29/78
CPC分类号： H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
摘要翻译：在各种实施例中，熔丝由硅化物形成，并且在翅片结构的翅片的顶部上形成。因为熔丝形成在翅片的顶部，所以它的宽度取得了非常薄的翅片的宽度。根据实施方案，保险丝也使用平面技术形成并且包括薄的宽度。因为保险丝的宽度较薄，所以能够可靠地使保险丝断开。此外，熔丝可以与晶体管一起使用以形成用于存储器阵列的存储单元，并且晶体管利用FinFET技术。

9. 发明申请

US20120243290A1 MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE 有权
标题翻译：使用一个编程器件的多级电气保险丝
公开(公告)号：US20120243290A1
公开(公告)日：2012-09-27
申请号：US13492635
申请日：2012-06-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/16
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

10. 发明授权

US08030181B2 Electrical fuse circuit for security applications 有权
标题翻译：电熔丝电路用于安全应用
公开(公告)号：US08030181B2
公开(公告)日：2011-10-04
申请号：US12881944
申请日：2010-09-14
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L21/326
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

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