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1. 发明授权

US08258602B2 Bipolar junction transistors having a fin 有权
标题翻译：具有翅片的双极结晶体管
公开(公告)号：US08258602B2
公开(公告)日：2012-09-04
申请号：US12618425
申请日：2009-11-13
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/73 , H01L21/823431
摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.
摘要翻译：描述用于制造双极结型晶体管的设计和方法。在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。第二翅片邻近并平行于第一翅片设置。第二鳍片包括与第一基底区域的第一接触。

2. 发明授权

US08957482B2 Electrical fuse and related applications 有权
标题翻译：电熔丝及相关应用
公开(公告)号：US08957482B2
公开(公告)日：2015-02-17
申请号：US12731325
申请日：2010-03-25
申请人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
发明人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
IPC分类号： H01L23/62 , H01L27/06 , H01L23/525 , H01L27/112 , H01L27/10 , H01L29/78
CPC分类号： H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
摘要翻译：在各种实施例中，熔丝由硅化物形成，并且在翅片结构的翅片的顶部上形成。因为熔丝形成在翅片的顶部，所以它的宽度取得了非常薄的翅片的宽度。根据实施方案，保险丝也使用平面技术形成并且包括薄的宽度。因为保险丝的宽度较薄，所以能够可靠地使保险丝断开。此外，熔丝可以与晶体管一起使用以形成用于存储器阵列的存储单元，并且晶体管利用FinFET技术。

3. 发明授权

US08305790B2 Electrical anti-fuse and related applications 有权
标题翻译：电抗保险丝及相关应用
公开(公告)号：US08305790B2
公开(公告)日：2012-11-06
申请号：US12724556
申请日：2010-03-16
申请人： Tao-Wen Chung , Po-Yao Ke , Shine Chung , Fu-Lung Hsueh
发明人： Tao-Wen Chung , Po-Yao Ke , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/00
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/112 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.
摘要翻译： FinFET晶体管的第一端子和第二端子用作反熔丝的两个端子。为了对反熔丝进行编程，控制FinFET晶体管的栅极，并且将具有预定幅度和预定持续时间的电压施加到第一端子，以使第一端子与第二端子电短路。

4. 发明授权

US08703571B2 Methods of fabricating bipolar junction transistors having a fin 有权
标题翻译：制造具有翅片的双极结型晶体管的方法
公开(公告)号：US08703571B2
公开(公告)日：2014-04-22
申请号：US13535090
申请日：2012-06-27
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L21/331
CPC分类号： H01L29/73 , H01L21/823431
摘要： A method of forming a semiconductor device is provided. The method includes forming a first fin above a substrate, forming a first emitter region in a first portion of the first fin, forming a first collector region in a second portion of the first fin, and forming a first base region in a third portion of the first fin. The third portion of the first fin is disposed underneath a first gate electrode. The method further includes forming a second fin adjacent to the first fin and above the substrate. The second fin is composed of a semiconductor material. The method also includes forming a first base contact over the second fin. The first base contact is coupled to the first base region through the second fin, the substrate, and the first fin.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在衬底上形成第一鳍片，在第一鳍片的第一部分中形成第一发射极区域，在第一鳍片的第二部分形成第一集电极区域，并在第三鳍片的第三部分形成第一基底区域第一个翅膀第一鳍片的第三部分设置在第一栅电极下方。该方法还包括形成邻近第一鳍片和衬底上方的第二鳍片。第二鳍由半导体材料构成。该方法还包括在第二翅片上形成第一基底接触。第一基底接触件通过第二鳍片，基底和第一鳍片耦合到第一基底区域。

5. 发明申请

US20120264269A1 Bipolar Junction Transistors and Methods of Fabrication Thereof 有权
标题翻译：双极结晶体管及其制造方法
公开(公告)号：US20120264269A1
公开(公告)日：2012-10-18
申请号：US13535090
申请日：2012-06-27
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L21/8222
CPC分类号： H01L29/73 , H01L21/823431
摘要： A method of forming a semiconductor device is provided. The method includes forming a first fin above a substrate, forming a first emitter region in a first portion of the first fin, forming a first collector region in a second portion of the first fin, and forming a first base region in a third portion of the first fin. The third portion of the first fin is disposed underneath a first gate electrode. The method further includes forming a second fin adjacent to the first fin and above the substrate. The second fin is composed of a semiconductor material. The method also includes forming a first base contact over the second fin. The first base contact is coupled to the first base region through the second fin, the substrate, and the first fin.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在衬底上形成第一鳍片，在第一鳍片的第一部分中形成第一发射极区域，在第一鳍片的第二部分中形成第一集电极区域，并在第三鳍片的第三部分形成第一基底区域第一个翅膀第一鳍片的第三部分设置在第一栅电极下方。该方法还包括形成邻近第一鳍片和衬底上方的第二鳍片。第二鳍由半导体材料构成。该方法还包括在第二翅片上形成第一基底接触。第一基底接触件通过第二鳍片，基底和第一鳍片耦合到第一基底区域。

6. 发明申请

US20100187656A1 Bipolar Junction Transistors and Methods of Fabrication Thereof 有权
标题翻译：双极结晶体管及其制造方法
公开(公告)号：US20100187656A1
公开(公告)日：2010-07-29
申请号：US12618425
申请日：2009-11-13
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L29/73
CPC分类号： H01L29/73 , H01L21/823431
摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.
摘要翻译：描述用于制造双极结型晶体管的设计和方法。在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。第二翅片邻近并平行于第一翅片设置。第二鳍片包括与第一基底区域的第一接触。

7. 发明申请

US20100327148A1 CMOS Image Sensors Formed of Logic Bipolar Transistors 有权
标题翻译： CMOS图像传感器由逻辑双极晶体管组成
公开(公告)号：US20100327148A1
公开(公告)日：2010-12-30
申请号：US12751552
申请日：2010-03-31
申请人： Shine Chung , Tao-Wen Chung , Fu-Lung Hsueh
发明人： Shine Chung , Tao-Wen Chung , Fu-Lung Hsueh
IPC分类号： H01L27/146 , H01L31/11 , H01L31/101
CPC分类号： H01L27/14609 , H01L27/14601 , H01L27/14643 , H01L31/0352
摘要： An integrated circuit structure includes an image sensor cell, which further includes a photo transistor configured to sense light and to generate a current from the light.
摘要翻译：集成电路结构包括图像传感器单元，其还包括被配置为感测光并从光产生电流的光电晶体管。

8. 发明授权

US08450672B2 CMOS image sensors formed of logic bipolar transistors 有权
标题翻译： CMOS图像传感器由逻辑双极晶体管组成
公开(公告)号：US08450672B2
公开(公告)日：2013-05-28
申请号：US12751552
申请日：2010-03-31
申请人： Shine Chung , Tao-Wen Chung , Fu-Lung Hsueh
发明人： Shine Chung , Tao-Wen Chung , Fu-Lung Hsueh
IPC分类号： H01L27/146 , H01L31/101
CPC分类号： H01L27/14609 , H01L27/14601 , H01L27/14643 , H01L31/0352
摘要： An integrated circuit structure includes an image sensor cell, which further includes a photo transistor configured to sense light and to generate a current from the light.
摘要翻译：集成电路结构包括图像传感器单元，其还包括被配置为感测光并从光产生电流的光电晶体管。

9. 发明授权

US08698566B2 Phase locked loop calibration 有权
标题翻译：锁相环校准
公开(公告)号：US08698566B2
公开(公告)日：2014-04-15
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
IPC分类号： H03L7/085 , H03L7/10 , H03B5/12
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译：电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。校准电路包括两个比较器，并向LCVCO提供粗调信号。两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。粗调频率范围大于微调频率范围。

10. 发明授权

US08432204B1 Current-controlled oscillator (CCO) based PLL 有权
标题翻译：基于电流控制振荡器（CCO）的PLL
公开(公告)号：US08432204B1
公开(公告)日：2013-04-30
申请号：US13344637
申请日：2012-01-06
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Yuwen Swei , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Yuwen Swei , Fu-Lung Hsueh
IPC分类号： H03L7/06
CPC分类号： H03L7/102 , H03L7/099 , H03L7/104
摘要： A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.
摘要翻译： PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴点连续可调。

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