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1. 发明授权

US08865528B2 Thin film transistor substrate and the method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08865528B2
公开(公告)日：2014-10-21
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

2. 发明申请

US20120064678A1 MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：薄膜晶体管阵列的制造方法
公开(公告)号：US20120064678A1
公开(公告)日：2012-03-15
申请号：US13069070
申请日：2011-03-22
申请人： Byeong-Jin LEE , Yu-Gwang Jeong , Dong-Ju Yang , Bong-Kyun Kim , Hong-Sick Park , Byeong-Beom Kim , Sang-Gab Kim , Ji-Young Park , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi
发明人： Byeong-Jin LEE , Yu-Gwang Jeong , Dong-Ju Yang , Bong-Kyun Kim , Hong-Sick Park , Byeong-Beom Kim , Sang-Gab Kim , Ji-Young Park , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/458 , H01L29/4908 , H01L29/66765 , H01L29/78678
摘要： A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact.
摘要翻译：一种TFT阵列板的制造方法，其特征在于，在金属层的第一和第二部分中形成具有第一和第二部分的感光膜图案，使用所述膜图案作为掩模蚀刻第三部分的金属层，以形成第一和第二金属蚀刻薄膜图案以去除第一部分，使用第二部分作为掩模蚀刻第三部分的第一和第二非晶硅层以形成非晶硅图案和半导体，蚀刻第一部分的第一和第二金属图案使用第二部分作为掩模形成源电极和包括上层和下层的漏极，并且通过使用第二部分作为掩模来蚀刻与第一部分相对应的区域的非晶硅图案以形成欧姆接触。

3. 发明申请

US20110133193A1 THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF 有权
标题翻译：薄膜晶体管基板及其方法
公开(公告)号：US20110133193A1
公开(公告)日：2011-06-09
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L27/12 , H01L29/786 , H01L21/336
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

4. 发明授权

US08450737B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08450737B2
公开(公告)日：2013-05-28
申请号：US12784376
申请日：2010-05-20
申请人： Shin-Il Choi , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
发明人： Shin-Il Choi , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
IPC分类号： H01L31/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
摘要翻译：薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法晶体管防止在信号线上形成异物。

5. 发明授权

US08476123B2 Method for manufacturing thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US08476123B2
公开(公告)日：2013-07-02
申请号：US13109686
申请日：2011-05-17
申请人： Dong-Ju Yang , Yu-Gwang Jeong , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi , Tae-Woo Kim
发明人： Dong-Ju Yang , Yu-Gwang Jeong , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi , Tae-Woo Kim
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L21/32138 , H01L27/1214 , H01L27/1255 , H01L29/458
摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.
摘要翻译：薄膜晶体管阵列板的制造方法包括：形成栅极线; 在栅极线上形成绝缘层; 第一和第二硅层第一和第二金属层; 形成具有第一和第二部分的光致抗蚀剂图案; 通过蚀刻第一和第二金属层来形成第一和第二金属图案; 用SF6或SF6 / He处理第一金属图案; 通过蚀刻第二和第一硅层形成硅和半导体图案; 去除光致抗蚀剂图案的第一部分; 通过湿法蚀刻第二金属图案形成数据线的上层; 通过蚀刻第一金属和非晶硅图案形成数据线的下层和欧姆接触; 在上层形成包括接触孔的钝化层; 以及在所述钝化层上形成像素电极。

6. 发明申请

US20090115066A1 Metal wiring layer and method of fabricating the same 有权
标题翻译：金属布线层及其制造方法
公开(公告)号：US20090115066A1
公开(公告)日：2009-05-07
申请号：US12290594
申请日：2008-10-31
申请人： Dong-Ju Yang , Shin-Il Choi , Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin , Ki-Yeup Lee , Yu-Gwang Jeong , Seung-Ha Choi
发明人： Dong-Ju Yang , Shin-Il Choi , Sang-Gab Kim , Min-Seok Oh , Hong-Kee Chin , Ki-Yeup Lee , Yu-Gwang Jeong , Seung-Ha Choi
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/535 , H01L21/743 , H01L27/1218 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display.
摘要翻译：提供金属布线层和制造金属布线层的方法。该方法包括在衬底上形成电介质层，通过蚀刻介电层的一部分，在衬底上形成多个介电层图案和孔，电介质层图案中的孔的横截面积随距离的增加而减小从衬底和暴露衬底的孔，通过蚀刻通过介电层图案中的孔暴露的衬底的一部分形成沟槽，以及形成填充沟槽和介电层图案中的空穴的金属层。因此，可以通过在电介质层图案中的多个孔中形成金属层来防止边缘积聚现象的发生，该电介质层图案的横截面积随离开距衬底的距离的增加而减小。因此，可以防止液晶层的透射率由于不能适当地填充液晶层中的液晶分子而降低，从而提高显示质量。

7. 发明授权

US08017459B2 Method of fabricating a thin film transistor array substrate 有权
标题翻译：制造薄膜晶体管阵列基板的方法
公开(公告)号：US08017459B2
公开(公告)日：2011-09-13
申请号：US12484116
申请日：2009-06-12
申请人： Dong-Ju Yang , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
发明人： Dong-Ju Yang , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
IPC分类号： H01L21/00
CPC分类号： H01L27/1248 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/7869
摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.
摘要翻译：提出了制造薄膜晶体管阵列基板的方法。该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到作为数据互连线的延伸线的漏电极。在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。形成连接到漏电极的像素电极。两个钝化层具有相同的组成，但是在不同的温度下进行处理。还提出了以上述方式制备的薄膜晶体管。

8. 发明授权

US08946004B2 Contact portion of wire and manufacturing method thereof 有权
标题翻译：电线接触部分及其制造方法
公开(公告)号：US08946004B2
公开(公告)日：2015-02-03
申请号：US12544144
申请日：2009-08-19
申请人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L29/786 , H01L27/12 , G02F1/1362
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
摘要翻译：公开了布线的接触部分及其制造方法。根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及透明电极，设置在所述层间绝缘层上并连接到所述金属层，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切，并且金属层填充在下绝缘层被切下的部分。

9. 发明申请

US20100230679A1 CONTACT PORTION OF WIRE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：接线方式及其制造方法
公开(公告)号：US20100230679A1
公开(公告)日：2010-09-16
申请号：US12544144
申请日：2009-08-19
申请人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Snag-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Snag-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L29/786 , H01L29/49 , H01L21/28 , H01L21/336
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
摘要翻译：公开了布线的接触部分及其制造方法。根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及设置在所述层间绝缘层上且与所述金属层连接的透明电极，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切，并且金属层填充在下绝缘层被切下的部分。

10. 发明申请

US20100163862A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20100163862A1
公开(公告)日：2010-07-01
申请号：US12484116
申请日：2009-06-12
申请人： Dong-Ju YANG , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
发明人： Dong-Ju YANG , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
IPC分类号： H01L29/786 , H01L29/24 , H01L21/336
CPC分类号： H01L27/1248 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/7869
摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.
摘要翻译：提出了制造薄膜晶体管阵列基板的方法。该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到作为数据互连线的延伸线的漏电极。在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。形成连接到漏电极的像素电极。两个钝化层具有相同的组成，但是在不同的温度下进行处理。还提出了以上述方式制备的薄膜晶体管。

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