专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08946004B2 Contact portion of wire and manufacturing method thereof 有权
标题翻译：电线接触部分及其制造方法
公开(公告)号：US08946004B2
公开(公告)日：2015-02-03
申请号：US12544144
申请日：2009-08-19
申请人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L29/786 , H01L27/12 , G02F1/1362
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
摘要翻译：公开了布线的接触部分及其制造方法。根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及透明电极，设置在所述层间绝缘层上并连接到所述金属层，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切，并且金属层填充在下绝缘层被切下的部分。

2. 发明授权

US08643012B2 Display substrate and method for manufacturing the same 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US08643012B2
公开(公告)日：2014-02-04
申请号：US12952744
申请日：2010-11-23
申请人： Min-Seok Oh , Bong-Kyu Shin , Sang-Gab Kim , Eun-Guk Lee , Hong-Kee Chin , Yu-Gwang Jeong , Seung-Ha Choi
发明人： Min-Seok Oh , Bong-Kyu Shin , Sang-Gab Kim , Eun-Guk Lee , Hong-Kee Chin , Yu-Gwang Jeong , Seung-Ha Choi
IPC分类号： H01L29/04
CPC分类号： G02F1/136227 , G02F1/13439 , G02F2201/50
摘要： A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask, Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.
摘要翻译：形成显示基板的方法包括在基板上形成阵列层，在阵列层上形成钝化层，在对应于栅极线，源极线和薄膜晶体管的钝化层上形成光致抗蚀剂图案使用光致抗蚀剂图案作为掩模蚀刻钝化层，对光致抗蚀剂图案的表面进行不均匀的表面处理，在其上形成有表面处理的光致抗蚀剂图案的基板上形成透明电极层并形成像素电极。形成像素电极包括通过将带状溶液浸入表面处理的光致抗蚀剂图案中去除光致抗蚀剂图案和透明电极层。

3. 发明授权

US08273612B2 Display panel and method of manufacturing the same 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US08273612B2
公开(公告)日：2012-09-25
申请号：US12981287
申请日：2010-12-29
申请人： Min-Seok Oh , Yang-Ho Bae , Pil-Sang Yun , Byeong-Beom Kim , Seung-Ha Choi , Sang-Gab Kim , Chang-Ho Jeong , Shin-Il Choi , Hong-Kee Chin , Yu-Gwang Jeong , Dong-Ju Yang
发明人： Min-Seok Oh , Yang-Ho Bae , Pil-Sang Yun , Byeong-Beom Kim , Seung-Ha Choi , Sang-Gab Kim , Chang-Ho Jeong , Shin-Il Choi , Hong-Kee Chin , Yu-Gwang Jeong , Dong-Ju Yang
IPC分类号： H01L21/84
CPC分类号： H01L27/12 , G02F2001/136295 , H01L27/124 , H01L29/458
摘要： In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.
摘要翻译：在显示面板和制造显示面板的方法中，在构成显示面板的基板上形成包括与数据线相同材料的栅极线，数据线以及源极和漏极，并且数据线包括铝基合金含有足够的镍以在干蚀刻期间抑制腐蚀。含有AlNi的合金的耐腐蚀性有助于防止在形成这些线和电极的选择性干蚀刻期间数据线，源电极和漏电极的腐蚀。

4. 发明申请

US20120003768A1 THIN FLIM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄片晶体管基板及其制造方法
公开(公告)号：US20120003768A1
公开(公告)日：2012-01-05
申请号：US13231225
申请日：2011-09-13
申请人： Hong-Kee CHIN , Sang-Gab KIM , Woong-Kwon KIM , Yong-Mo CHOI , Seung-Ha CHOI , Shin-Il CHOI , Ho-Jun LEE , Jung-Suk BANG , Yu-Gwang JEONG
发明人： Hong-Kee CHIN , Sang-Gab KIM , Woong-Kwon KIM , Yong-Mo CHOI , Seung-Ha CHOI , Shin-Il CHOI , Ho-Jun LEE , Jung-Suk BANG , Yu-Gwang JEONG
IPC分类号： H01L33/16
CPC分类号： H01L27/12 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.
摘要翻译：提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

5. 发明授权

US08067774B2 Thin film transistor panel and method of manufacturing the same 有权
标题翻译：薄膜晶体管面板及其制造方法
公开(公告)号：US08067774B2
公开(公告)日：2011-11-29
申请号：US12434942
申请日：2009-05-04
申请人： Seung-Ha Choi , Ki-Yeup Lee , Sang-Gab Kim , Shin-il Choi , Dong-Ju Yang , Hong-Kee Chin , Yu-Gwang Jeong , Ji-Young Park , Dong-Hoon Lee , Byeong-Beom Kim
发明人： Seung-Ha Choi , Ki-Yeup Lee , Sang-Gab Kim , Shin-il Choi , Dong-Ju Yang , Hong-Kee Chin , Yu-Gwang Jeong , Ji-Young Park , Dong-Hoon Lee , Byeong-Beom Kim
IPC分类号： H01L27/14
CPC分类号： H01L29/458 , H01L27/124 , H01L29/4908
摘要： After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.
摘要翻译：在形成包括铝的信号线之后，在相同的室中形成包含覆盖信号线的铝的氧化物层的上层，并且通过使用与信号线相同的溅射靶，或者包括铝的氧化物层的缓冲层形成在接触孔形成期间暴露信号线的接触孔中。因此，可以改善包括氧化铟锡（“ITO”）或氧化铟锌（“IZO”）的上层与信号线之间的接触特性，以增强其之间的粘附，同时不增加薄膜晶体管的生产成本（“TFT”）阵列面板。

6. 发明授权

US08044405B2 Thin film transistor substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08044405B2
公开(公告)日：2011-10-25
申请号：US12429388
申请日：2009-04-24
申请人： Hong-Kee Chin , Sang-Gab Kim , Woong-Kwon Kim , Yong-Mo Choi , Seung-Ha Choi , Shin-Il Choi , Ho-Jun Lee , Jung-Suk Bang , Yu-Gwang Jeong
发明人： Hong-Kee Chin , Sang-Gab Kim , Woong-Kwon Kim , Yong-Mo Choi , Seung-Ha Choi , Shin-Il Choi , Ho-Jun Lee , Jung-Suk Bang , Yu-Gwang Jeong
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L27/12 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.
摘要翻译：提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

7. 发明申请

US20110133193A1 THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF 有权
标题翻译：薄膜晶体管基板及其方法
公开(公告)号：US20110133193A1
公开(公告)日：2011-06-09
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L27/12 , H01L29/786 , H01L21/336
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

8. 发明申请

US20100230679A1 CONTACT PORTION OF WIRE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：接线方式及其制造方法
公开(公告)号：US20100230679A1
公开(公告)日：2010-09-16
申请号：US12544144
申请日：2009-08-19
申请人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Snag-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Snag-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L29/786 , H01L29/49 , H01L21/28 , H01L21/336
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
摘要翻译：公开了布线的接触部分及其制造方法。根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及设置在所述层间绝缘层上且与所述金属层连接的透明电极，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切，并且金属层填充在下绝缘层被切下的部分。

9. 发明授权

US07758760B2 Thin film transistor array panel and method of manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07758760B2
公开(公告)日：2010-07-20
申请号：US11544987
申请日：2006-10-06
申请人： Seung-Ha Choi , Min-Seok Oh , Hong-Kee Chin , Sang-Gab Kim , Yu-Gwang Jeong
发明人： Seung-Ha Choi , Min-Seok Oh , Hong-Kee Chin , Sang-Gab Kim , Yu-Gwang Jeong
IPC分类号： B44C1/22
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.
摘要翻译：提供薄膜晶体管（TFT）阵列面板及其制造方法。该方法包括在栅极线上形成半导体层和欧姆接触层，在欧姆接触层上形成导电层，在导电层上形成第一感光层图案，使用第一感光层图案蚀刻导电层，作为蚀刻掩模，使用第一感光层图案作为蚀刻掩模，通过含氟气体，含氯气体和氧（O 2）气蚀刻欧姆接触层和半导体层，将第一感光层图案去除预定厚度以形成第二感光层图案，并且使用第二感光层图案蚀刻导电层作为蚀刻掩模以暴露欧姆接触层的一部分。

10. 发明申请

US20100163862A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20100163862A1
公开(公告)日：2010-07-01
申请号：US12484116
申请日：2009-06-12
申请人： Dong-Ju YANG , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
发明人： Dong-Ju YANG , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
IPC分类号： H01L29/786 , H01L29/24 , H01L21/336
CPC分类号： H01L27/1248 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/7869
摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.
摘要翻译：提出了制造薄膜晶体管阵列基板的方法。该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到作为数据互连线的延伸线的漏电极。在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。形成连接到漏电极的像素电极。两个钝化层具有相同的组成，但是在不同的温度下进行处理。还提出了以上述方式制备的薄膜晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式