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1. 发明授权

US08643078B2 Semiconductor structure and manufacturing method of the same 有权
标题翻译：半导体结构及其制造方法相同
公开(公告)号：US08643078B2
公开(公告)日：2014-02-04
申请号：US13443417
申请日：2012-04-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/788
CPC分类号： H01L23/3192 , H01L27/11565 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基极，层叠结构和掺杂层。堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和第一侧壁的长边缘沿着通道方向延伸。掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

2. 发明授权

US08704205B2 Semiconductor structure with improved capacitance of bit line 有权
标题翻译：具有改善位线电容的半导体结构
公开(公告)号：US08704205B2
公开(公告)日：2014-04-22
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

3. 发明申请

US20130264683A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20130264683A1
公开(公告)日：2013-10-10
申请号：US13443417
申请日：2012-04-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/00 , H01L21/56
CPC分类号： H01L23/3192 , H01L27/11565 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基极，层叠结构和掺杂层。堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和第一侧壁的长边缘沿着通道方向延伸。掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

4. 发明授权

US09240405B2 Memory with off-chip controller 有权
标题翻译：具有片外控制器的内存
公开(公告)号：US09240405B2
公开(公告)日：2016-01-19
申请号：US13089652
申请日：2011-04-19
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L27/118 , H01L27/06 , H01L27/02 , H01L27/105 , H01L27/115
CPC分类号： H01L27/0688 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11578
摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.
摘要翻译：描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。然后可以将单独的电路堆叠并结合在一起。

5. 发明申请

US20120267689A1 Memory with Off-Chip Controller 有权
标题翻译：具有片外控制器的存储器
公开(公告)号：US20120267689A1
公开(公告)日：2012-10-25
申请号：US13089652
申请日：2011-04-19
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/0688 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11578
摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.
摘要翻译：描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。然后可以将单独的电路堆叠并结合在一起。

6. 发明申请

US20140054535A1 SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
标题翻译：具有改进位线电容的半导体结构
公开(公告)号：US20140054535A1
公开(公告)日：2014-02-27
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

7. 发明授权

US08324681B2 Stacked non-volatile memory device and methods for fabricating the same 有权
标题翻译：堆叠的非易失性存储器件及其制造方法
公开(公告)号：US08324681B2
公开(公告)日：2012-12-04
申请号：US13162386
申请日：2011-06-16
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/792
摘要： A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.
摘要翻译：堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。该器件可以配置为NAND操作。

8. 发明申请

US20070037328A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20070037328A1
公开(公告)日：2007-02-15
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

9. 发明授权

US08846549B2 Method of forming bottom oxide for nitride flash memory 有权
标题翻译：形成氮化物闪存底部氧化物的方法
公开(公告)号：US08846549B2
公开(公告)日：2014-09-30
申请号：US11235786
申请日：2005-09-27
申请人： Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/31 , G11C16/04 , H01L21/28 , H01L29/51
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513
摘要： A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.
摘要翻译：半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。底部氧化物层可以具有高达5E19cm-3的氢浓度和高达5E11cm-2eV-1的界面陷阱密度。三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。

10. 发明授权

US07999295B2 Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same 有权
标题翻译：叠层薄膜晶体管，非易失性存储器件及其制造方法
公开(公告)号：US07999295B2
公开(公告)日：2011-08-16
申请号：US12337289
申请日：2008-12-17
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11578 , H01L27/1203 , H01L29/4234
摘要： A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.
摘要翻译：用于堆叠的非易失性存储器件的制造方法提供具有电荷俘获结构的多个位线层和字线层。位线层具有形成在绝缘层上的多个位线，例如绝缘体上硅技术。用相应的多个字线和与位线正交的电荷俘获结构对字线层进行构图。

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