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    • 9. 发明授权
    • Semiconductor structure with improved capacitance of bit line
    • 具有改善位线电容的半导体结构
    • US08704205B2
    • 2014-04-22
    • US13594353
    • 2012-08-24
    • Shih-Hung ChenHang-Ting LueKuang-Yeu HsiehErh-Kun LaiYen-Hao Shih
    • Shih-Hung ChenHang-Ting LueKuang-Yeu HsiehErh-Kun LaiYen-Hao Shih
    • H01L47/00
    • H01L27/11582H01L27/11548H01L27/11556H01L27/11575
    • A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
    • 具有改善的位线电容的半导体结构包括衬底,堆叠存储器结构,多个位线,第一阶梯接触结构,第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上,并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中,其中位线通过,然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。