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1. 发明申请

US20090075466A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090075466A1
公开(公告)日：2009-03-19
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

2. 发明授权

US07977227B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07977227B2
公开(公告)日：2011-07-12
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

3. 发明授权

US07414282B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07414282B2
公开(公告)日：2008-08-19
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

4. 发明申请

US20070037328A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20070037328A1
公开(公告)日：2007-02-15
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

5. 发明授权

US07605079B2 Manufacturing method for phase change RAM with electrode layer process 有权
标题翻译：具有电极层工艺的相变RAM的制造方法
公开(公告)号：US07605079B2
公开(公告)日：2009-10-20
申请号：US11382799
申请日：2006-05-11
申请人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
IPC分类号： H01L21/44
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process scaling with shrinking critical dimensions for metallization layers. The electrode layer is made by forming a multi-layer dielectric layer on a substrate, etching the multi-layer dielectric layer to form vias for electrode members contacting circuitry below, forming insulating spacers on the vias, etching through a top layer in the multi-layer dielectric layer to form trenches between the insulating spacers for electrode members contacting circuitry above, filling the vias and trenches with a conductive material using the metallization process. Thin film bridges of memory material are formed over the electrode layer.
摘要翻译：一种相变存储器件的制造方法，包括形成电极层。使用导体填充技术在电极层中制造电极，该技术也用于金属化层的层间导体，以便通过金属化层的缩小临界尺寸改善工艺规模。电极层是通过在衬底上形成多层电介质层而形成的，蚀刻多层电介质层以形成接触下面电路的电极构件的通路，在通孔上形成绝缘隔离层，以在用于接触上述电路的电极部件的绝缘间隔物之间形成沟槽，用导电材料使用金属化工艺填充过孔和沟槽。存储材料的薄膜桥形成在电极层上。

6. 发明授权

US07599217B2 Memory cell device and manufacturing method 有权
标题翻译：存储单元器件及其制造方法
公开(公告)号：US07599217B2
公开(公告)日：2009-10-06
申请号：US11357902
申请日：2006-02-17
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1691
摘要： A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also discussed.
摘要翻译：具有可通过施加能量在电性能状态之间切换的记忆材料的存储单元装置包括电极，与电极表面相对的分离层，分离层中的孔，孔中的第二材料限定具有向下和向内逐渐变细的空隙区域。记忆材料位于与电极表面电接触的空隙区域中。第二电极与记忆材料电接触。在第一和第二电极之间的能量通过集中在存储材料内，以便于改变存储材料的电性能状态。记忆材料可以包括相变材料。第二材料可以包括高密度等离子体沉积材料。还讨论了制造存储单元器件的方法。

7. 发明申请

US20090239358A1 Memory Device Manufacturing Method 有权
标题翻译：存储器件制造方法
公开(公告)号：US20090239358A1
公开(公告)日：2009-09-24
申请号：US12469184
申请日：2009-05-20
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/28
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.
摘要翻译：制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。第一和第二电极形成在第一和第二表面上。存储元件形成在表面段上以电连接第一和第二电极。

8. 发明申请

US20090148981A1 METHOD FOR FORMING SELF-ALIGNED THERMAL ISOLATION CELL FOR A VARIABLE RESISTANCE MEMORY ARRAY 有权
标题翻译：形成可变电阻记忆阵列的自对准热隔离单元的方法
公开(公告)号：US20090148981A1
公开(公告)日：2009-06-11
申请号：US12351692
申请日：2009-01-09
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1683
摘要： A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.
摘要翻译：具有自对准RRAM元件的非易失性存储器包括具有内接触表面的大体平面形状的下电极元件; 与所述下电极元件间隔开的上电极元件; 容纳结构在上电极元件和下电极元件之间延伸，侧壁间隔元件具有大致漏斗形的具有中心孔的中心腔; 以及位于侧壁间隔元件和下电极之间的突出元件。 RRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔件元件中心腔的至少一部分并且从侧壁间隔件端子边缘朝向和与下电极接触。以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

9. 发明申请

US20080157053A1 Resistor Random Access Memory Cell Device 有权
标题翻译：电阻随机存取存储单元装置
公开(公告)号：US20080157053A1
公开(公告)日：2008-07-03
申请号：US11617542
申请日：2006-12-28
申请人： Erh Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L47/00
CPC分类号： H01L45/122 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.
摘要翻译：存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件材料。因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

10. 发明授权

US07989790B2 Resistance random access memory 有权
标题翻译：电阻随机存取存储器
公开(公告)号：US07989790B2
公开(公告)日：2011-08-02
申请号：US11656246
申请日：2007-01-18
申请人： Erh-Kun Lai , Chiahua Ho , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang-Yeu Hsieh
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C16/0475 , G11C2213/31 , G11C2213/51
摘要： A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.
摘要翻译：存储器包括在第一方向上的多个字线，第二方向上的多个位线，每个字线连接到至少一个字线，以及多个存储器元件，每个存储器元件耦合到字线之一，其中一个位线。每个存储元件包括用于连接到对应的字线的顶部电极，用于连接到对应的位线的底部电极，底部电极上的电阻层，以及至少两个分离的衬垫，每个衬垫在两端具有电阻材料衬垫和每个衬垫耦合在顶部电极和电阻层之间。

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