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    • 3. 发明授权
    • Architecture of an integrated circuit for streaming media over wireless networks
    • 无线网络流媒体集成电路架构
    • US07263080B1
    • 2007-08-28
    • US11279881
    • 2006-04-15
    • Robin Yubin ZhuChung-Hsing ChangTed Hsiung
    • Robin Yubin ZhuChung-Hsing ChangTed Hsiung
    • H04Q7/00
    • H04L1/0054H04L1/0065H04L27/2628H04L27/2647H04W88/06
    • An integrated circuit for streaming media over wireless networks is disclosed. The integrated circuit includes a media module that is designed to process media data. When non-media data is in, switching means is provided to avoid the non-media data being processed in the media module. One of important features in the integrated circuit is the underlying designs that are capable of facilitating wireless communication in different wireless networks. In one embodiment, a baseband processor is provided to facilitate wireless communications in more than one standard. The baseband processor is uniquely designed to facilitate wireless communications in a Wi-Fi network as well as a WiMAX network. As a result, same chips may be used to stream media data across different wireless networks.
    • 公开了一种用于通过无线网络流媒体的集成电路。 集成电路包括被设计为处理媒体数据的媒体模块。 当非媒体数据进入时,提供切换装置以避免在媒体模块中处理非媒体数据。 集成电路的重要特征之一是能够促进不同无线网络中的无线通信的底层设计。 在一个实施例中,提供基带处理器以促进多于一个标准中的无线通信。 基带处理器是独特的设计,以促进Wi-Fi网络以及WiMAX网络中的无线通信。 因此,可以使用相同的芯片来跨越不同的无线网络流媒体数据。
    • 4. 发明授权
    • Combined system for producing error correction code symbols and error syndromes
    • 用于产生纠错码符号和错误综合征的组合系统
    • US06260173B1
    • 2001-07-10
    • US09219472
    • 1998-12-23
    • Lih-Jyh WengBa-Zhong ShenShih MoChung-Hsing Chang
    • Lih-Jyh WengBa-Zhong ShenShih MoChung-Hsing Chang
    • H03M1300
    • H03M13/158H03M13/1515
    • A combined encoding/syndrome generating circuit is segmented into multiple-cell blocks that operate in parallel during encoding operations to produce interim sums. The interim sums are then combined to propagate a sum across the system, from the first cell to the last cell. Each cell includes a Galois Field multiplier and an associated update adder and register. A block of two cells includes two sets of associated Galois Field multipliers, registers and update adders, and a block feedback adder that produces the associated interim sum by adding together the products produced in parallel by each of the cells. A block with more than two cells includes additional feedback adders that operate in parallel to selectively combine the products produced by the plurality of cells, and produce an interim sum that includes a contribution from each of the cells in the block. The system then adds together the interim sums produced simultaneously by the various blocks, to propagate a sum across the system. Also, the interim sum from a given block is combined in parallel into the products produced by the respective cells of the next block, to include in the update signals that are fed back to the associated registers the contributions from each of the previous cells. During syndrome generation operations, the cells essentially operate independently to produce the syndromes. The current system includes more feedback adders than the conventional Fettweis-Hassner circuit, however, the delay through the current system is reduced from that of the conventional system, since many of the feedback adders in the current system operate in parallel.
    • 组合编码/校正子产生电路被分割成在编码操作期间并行操作以产生临时和的多小区块。 然后组合中间和以在整个系统上传播一个从第一个单元到最后一个单元的和。 每个单元包括伽罗瓦域乘法器和相关联的更新加法器和寄存器。 两个单元的块包括两组相关联的伽罗瓦域乘法器,寄存器和更新加法器,以及块反馈加法器,其通过将由每个单元并行产生的乘积相加来产生相关联的临时和。 具有多于两个单元的块包括并行操作的选择性组合由多个单元产生的乘积的另外的反馈加法器,并且产生包括来自块中的每个单元的贡献的中间和。 然后,该系统将由各个块同时产生的临时总和相加,以在系统上传播和。 此外,来自给定块的中间和并行组合为由下一个块的相应小区产生的产品,以将在反馈到相关联的寄存器的更新信号中包括来自每个先前小区的贡献。 在综合征发生过程中,细胞基本上独立运作以产生综合征。 目前的系统包括比传统的Fettweis-Hassner电路更多的反馈加法器,然而,通过当前系统的延迟比常规系统的延迟减小,因为当前系统中的许多反馈加法器并行操作。
    • 6. 发明申请
    • Charging Method And Charging Device For Charging A Rechargeable Battery
    • 充电方法和充电装置为充电电池充电
    • US20110285359A1
    • 2011-11-24
    • US12785145
    • 2010-05-21
    • Chung-Hsing ChangWen-Yi ChenChia-Liang Lin
    • Chung-Hsing ChangWen-Yi ChenChia-Liang Lin
    • H02J7/04
    • H02J7/0083
    • A charging method fit for use with and applicable to a rechargeable battery is provided. The charging method involves charging the rechargeable battery to a first preset voltage and then charging the rechargeable battery to a second preset voltage. The charging method includes the steps of: (a) using the first preset current as a charging current, and performing the constant current charging of the rechargeable battery by the first preset current until the rechargeable battery reaches the first preset voltage for the first instance; (b) subtracting a current difference value from the charging current used by the rechargeable battery to reach the first preset voltage in the preceding instance so as to obtain a new charging current, and performing the constant current charging of the rechargeable battery by the new charging current thus obtained until the rechargeable battery reaches the first preset voltage again; (c) repeating step (b) until the new charging current equals a second preset current; and step (d) using the second preset current of step (c) as another new charging current, and performing the constant current charging of the rechargeable battery by the second preset current until the rechargeable battery reaches a second preset voltage for the first instance.
    • 提供适用于可充电电池的充电方法。 充电方法包括将可再充电电池充电到第一预设电压,然后将可再充电电池充电到第二预设电压。 充电方法包括以下步骤:(a)使用第一预置电流作为充电电流,并且通过第一预设电流执行可再充电电池的恒定电流充电直到可再充电电池首次达到第一预置电压; (b)从先前的例子中减去由可再充电电池使用的充电电流达到第一预设电压的电流差值,以获得新的充电电流,并通过新充电来执行可再充电电池的恒定电流充电 直到可再充电电池再次达到第一预置电压为止; (c)重复步骤(b),直到新的充电电流等于第二预设电流; 和步骤(d)使用步骤(c)的第二预设电流作为另一新的充电电流,并且通过第二预设电流执行可再充电电池的恒定电流充电,直到可再充电电池达到第一预定电压为止。
    • 7. 发明授权
    • Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution ERA
    • 全尺寸散射棒alt-PSM技术用于分辨率ERA中的IC制造
    • US07013453B2
    • 2006-03-14
    • US10781176
    • 2004-02-18
    • Chang-Ming DaiChung-Hsing ChangJan-Wen YouBurn J. Lin
    • Chang-Ming DaiChung-Hsing ChangJan-Wen YouBurn J. Lin
    • G06F17/50
    • G03F1/32G03F1/30G03F1/70G03F7/2026
    • A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.
    • 描述了在制造集成电路期间同时缩小栅极长度和多晶硅互连的工艺。 正色调光致抗蚀剂涂覆在基板上,并且首先用具有全尺寸散射条的交替相移掩模曝光,这使得栅极尺寸能够被印刷为曝光波长尺寸的1/4至1/2。 然后使用具有镀铬阻挡区域的三次衰减相移掩模将衬底曝光,以保护收缩的栅极和具有散射棒的衰减区域以收缩互连线。 散射棒不会印在光刻胶图案中。 该方法比常规光刻方法提供更高的DOF,更低的OPE和更低的对透镜像差的灵敏度。 提供了数据处理流程,其导致针对两个掩模中的每一个的修改的GDS布局。 还包括用于生成相移布局数据的系统。
    • 8. 发明申请
    • Clear field annular type phase shifting mask
    • 透明环形型移相掩模
    • US20050123838A1
    • 2005-06-09
    • US10730533
    • 2003-12-08
    • Chung-Hsing ChangC. H. LinChung-Kuang Chen
    • Chung-Hsing ChangC. H. LinChung-Kuang Chen
    • G03F1/00G03F1/08G03F7/20G03F9/00H01L21/00
    • G03F1/34
    • A mask comprises a mask substrate and at least one annular equal line space phase shifting pattern on said mask substrate to produce an opaque region on a semiconductor substrate. A method of manufacturing a mask comprises providing a mask substrate; forming a layer of resist material on said substrate; patterning at least one annular equal line space phase shifting pattern on said resist layer; patterning said pattern onto said mask substrate; removing a remaining portion of said resist layer. A method of transferring a pattern onto a semiconductor substrate comprises illuminating a mask comprising at least one annular equal line space phase shifting pattern on the mask to produce an opaque region on a semiconductor substrate.
    • 掩模包括掩模基板和在所述掩模基板上的至少一个环形等行空间相移图案,以在半导体基板上产生不透明区域。 一种制造掩模的方法包括提供掩模基板; 在所述基板上形成抗蚀材料层; 在所述抗蚀剂层上形成至少一个环形等行空间相移图案; 将所述图案图案化成所述掩模基板; 去除所述抗蚀剂层的剩余部分。 将图案转移到半导体衬底上的方法包括在掩模上照射包括至少一个环形等行空间相移图案的掩模,以在半导体衬底上产生不透明区域。
    • 9. 发明授权
    • Contact printing as second exposure of double exposure attenuated phase shift mask process
    • 接触印刷作为双曝光衰减相移掩模工艺的第二曝光
    • US06861180B2
    • 2005-03-01
    • US10241675
    • 2002-09-10
    • Chung-Hsing Chang
    • Chung-Hsing Chang
    • G03B27/02G03C5/00G03F1/32G03F7/20G03F9/00
    • G03F1/32
    • Utilizing contact printing as the second exposure within a double exposure attenuated phase shift mask (APSM) fabrication process is disclosed. The process defines the shift pattern within the attenuated layer of the APSM using a first exposure, such as electron beam (e-beam) writing. The attenuated layer may be MoSi, MoSiO, and so on. The process then defines the border pattern within the opaque layer of the APSM using a second exposure. The second exposure employs contact printing, utilizing a contact exposure mask. The contact printing process may align the contact exposure mask over the wafer on which the APSM is fabricated utilizing a camera and an image storage system storing an image of this wafer.
    • 公开了在双曝光衰减相移掩模(APSM)制造工艺中利用接触印刷作为第二曝光。 该过程使用诸如电子束(电子束)写入的第一曝光来限定APSM的衰减层内的移动模式。 衰减层可以是MoSi,MoSiO等。 然后,该过程使用第二次曝光来限定APSM的不透明层内的边界图案。 第二次曝光采用接触印刷,利用接触曝光掩模。 接触印刷过程可以使用相机和存储该晶片的图像的图像存储系统将接触曝光掩模对准在其上制造APSM的晶片上。