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1. 发明授权

US5192943A Cursor display control method and apparatus in a graphic display system 失效
标题翻译：图形显示系统中的光标显示控制方法和装置
公开(公告)号：US5192943A
公开(公告)日：1993-03-09
申请号：US583584
申请日：1990-09-17
申请人： Shigeru Matsuo , Tadashi Fukushima , Tooru Komagawa , Masahisa Narita
发明人： Shigeru Matsuo , Tadashi Fukushima , Tooru Komagawa , Masahisa Narita
IPC分类号： G06F3/14 , G06F3/048 , G09G5/08
CPC分类号： G09G5/08
摘要： A cursor display control in a graphic display system is provided in which a storage range is provided for exclusive use for a cursor pattern and a desired shape is defined in the storage range to thereby perform a high-speed cursor movement. A display control apparatus in the graphic display system includes a memory for storing a cursor pattern, shift register for performing a shift processing in a non-display period of the cursor for positioning in the display screen, and parallel-serial converter for performing parallel to serial conversion at the display timing of the cursor, whereby the apparatus is suitable to be integrated in the form of an LSI and the cursor can be moved at a high speed on the screen.

2. 发明授权

US5507026A Address-translatable graphic processor, data processor and drawing method with employment of the same 失效
标题翻译：地址可翻译的图形处理器，数据处理器和绘图方法与使用相同
公开(公告)号：US5507026A
公开(公告)日：1996-04-09
申请号：US301016
申请日：1994-09-06
申请人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
发明人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
IPC分类号： G06F12/10 , G06T1/20 , G06F15/16
CPC分类号： G06T1/20 , G06F12/10
摘要： In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address so as to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit and graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.
摘要翻译：在图形处理系统中，提供了主存储器，包含用于保存显示数据的位图存储器的缓冲器，用于执行涉及从虚拟地址转换为物理地址的数据处理的中央处理单元，以访问主存储器，连接到主存储器和缓冲器的图形处理器，用于将数据处理成显示形式，以及连接到中央处理单元，主存储器和图形处理器的系统总线接口，能够在它们之间交换数据。此外，图形处理系统包括连接到系统总线接口的绘图处理单元，用于将虚拟地址转换为物理地址以访问主存储器并处理该数据;总线仲裁器，用于在需求之间执行仲裁从中央处理单元和图形处理器给出的接口，以及用于断言请求将接口释放到中央处理单元的信号的挂起电路。

3. 发明授权

US06229543B1 Microprocessor, and graphics processing apparatus and method using the same 失效
标题翻译：微处理器，以及使用其的图形处理装置和方法
公开(公告)号：US06229543B1
公开(公告)日：2001-05-08
申请号：US07511778
申请日：1990-04-20
申请人： Hiromichi Yamada , Tadashi Fukushima , Shigeru Matsuo , Takashi Miyamoto , Tooru Komagawa , Syoji Yoshida
发明人： Hiromichi Yamada , Tadashi Fukushima , Shigeru Matsuo , Takashi Miyamoto , Tooru Komagawa , Syoji Yoshida
IPC分类号： G06T100
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F15/7832 , G06T1/20
摘要： A microprocessor for processing a large quantity of graphics data. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. A graphics processing apparatus provided by the microprocessor transfers the graphics data between a system memory and a frame memory at high speeds.
摘要翻译：用于处理大量图形数据的微处理器。独立于CPU的微处理器具有两个端口，并且同时对安装在单独总线上的两个存储器执行指令获取和数据访问或存储器访问。由微处理器提供的图形处理装置以高速度在系统存储器和帧存储器之间传送图形数据。

4. 发明授权

US5664161A Address-translatable graphic processor, data processor and drawing method with employment of the same 失效
标题翻译：地址可翻译的图形处理器，数据处理器和绘图方法与使用相同
公开(公告)号：US5664161A
公开(公告)日：1997-09-02
申请号：US472741
申请日：1995-06-07
申请人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
发明人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
IPC分类号： G06F12/10 , G06T1/20 , G06F15/00 , G06T1/00
CPC分类号： G06T1/20 , G06F12/10
摘要： In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address so as to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit and graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.
摘要翻译：在图形处理系统中，提供了主存储器，包含用于保存显示数据的位图存储器的缓冲器，用于执行涉及从虚拟地址转换为物理地址的数据处理的中央处理单元，以访问主存储器，连接到主存储器和缓冲器的图形处理器，用于将数据处理成显示形式，以及连接到中央处理单元，主存储器和图形处理器的系统总线接口，能够在它们之间交换数据。此外，图形处理系统包括连接到系统总线接口的绘图处理单元，用于将虚拟地址转换为物理地址以访问主存储器并处理该数据;总线仲裁器，用于在需求之间执行仲裁从中央处理单元和图形处理器给出的接口，以及用于断言请求将接口释放到中央处理单元的信号的挂起电路。

5. 发明授权

US06727903B1 Microprocessor, and graphics processing apparatus and method using the same 失效
标题翻译：微处理器，以及使用其的图形处理装置和方法
公开(公告)号：US06727903B1
公开(公告)日：2004-04-27
申请号：US09414945
申请日：1999-10-08
申请人： Hiromichi Yamada , Tadashi Fukushima , Shigeru Matsuo , Takashi Miyamoto , Tooru Komagawa , Syoji Yoshida
发明人： Hiromichi Yamada , Tadashi Fukushima , Shigeru Matsuo , Takashi Miyamoto , Tooru Komagawa , Syoji Yoshida
IPC分类号： G06T100
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3879 , G06F15/7832 , G06T1/20
摘要： A microprocessor suitable for processing a large quantity of graphics data. Graphics processing apparatus and method using the microprocessor are also disclosed. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. In the graphics processing apparatus in which this microprocessor is employed, the graphics transfer between a system memory and a frame memory can be performed at higher speed.
摘要翻译：适用于处理大量图形数据的微处理器。还公开了使用微处理器的图形处理装置和方法。独立于CPU的微处理器具有两个端口，并且同时执行指令获取和数据访问或存储器访问，以安装在分开的总线上的两个存储器中。在图形处理装置使用该微处理器，可以以更高的速度执行系统存储器和帧存储器之间的图形传送。

6. 发明授权

US5369744A Address-translatable graphic processor, data processor and drawing method with employment of the same 失效
标题翻译：地址可翻译的图形处理器，数据处理器和绘图方法与使用相同
公开(公告)号：US5369744A
公开(公告)日：1994-11-29
申请号：US596366
申请日：1990-10-12
申请人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
发明人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
IPC分类号： G06F12/10 , G06T1/20 , G06F15/20
CPC分类号： G06T1/20 , G06F12/10
摘要： In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit add graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.
摘要翻译：在图形处理系统中，提供了主存储器，包含用于保存显示数据的位图存储器的缓冲器，用于执行涉及从虚拟地址到物理地址的转换以访问主存储器的数据处理的中央处理单元连接到主存储器和缓冲器的图形处理器，用于将数据处理成显示形式，以及连接到中央处理单元，主存储器和图形处理器的系统总线接口，能够在它们之间交换数据。此外，图形处理系统包括连接到系统总线接口的绘图处理单元，用于将虚拟地址转换为物理地址以访问主存储器并处理数据;总线仲裁器，用于在使用接口的需求之间执行仲裁从中央处理单元给出的图形处理器，以及用于断言请求将接口释放到中央处理单元的信号的挂起电路。

7. 发明授权

US4979103A Data processing method and apparatus having plural bus interfaces 失效
标题翻译：具有多个总线接口的数据处理方法和装置
公开(公告)号：US4979103A
公开(公告)日：1990-12-18
申请号：US176234
申请日：1988-03-31
申请人： Hiroyuki Kida , Tooru Komagawa , Hideo Maejima
发明人： Hiroyuki Kida , Tooru Komagawa , Hideo Maejima
IPC分类号： G06F9/30 , G06F15/78
CPC分类号： G06F15/786
摘要： A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.
摘要翻译：一种用于控制系统中的多个总线接口的方法和装置，包括在一个芯片上的中央处理单元和内部存储器。当鉴别位于芯片外部的一个操作数时，由第一操作数检索单元执行第一操作数检索操作，并且当鉴别位于芯片内的另一操作数时，由第二操作数检索单元执行第二操作数检索操作，使得操作数根据第一和第二操作数检索单元的总线接口信号读取到中央处理单元。

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