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1. 发明申请

WO2018005100A1 APPARATUSES, METHODS, AND SYSTEMS FOR PACKAGE ON PACKAGE MEMORY REFRESH AND SELF-REFRESH RATE MANAGEMENT 审中-公开
标题翻译：用于封装存储器刷新和自刷新率管理的装置，方法和系统
公开(公告)号：WO2018005100A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037514
申请日：2017-06-14
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , KULICK, Stanley S.
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G06F15/786 , G11C11/40615
摘要： Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.
摘要翻译：描述了与封装式存储器刷新和自刷新率管理相关的方法，系统和装置。在一个实施例中，一种装置包括处理器管芯，安装到处理器管芯并与处理器管芯重叠的动态存储器管芯，处理器管芯的第一热传感器与第一类型工作负载的第一热点相邻设置，以及第二热传感器为所述处理器管芯设置在来自第二类型工作负载的第二热点附近，以及所述处理器管芯的硬件控制电路，以在所述第一热传感器的输出中的任一者超过所述动态存储器管芯的电容器时使所述动态存储器管芯的电容器更新第一阈值和第二热传感器的输出超过第二阈值。

2. 发明申请

WO1992005496A1 EVENT SIGNALLING SYSTEM AND METHOD FOR PROCESSOR SYSTEM HAVING CENTRAL MEMORY UNIT 审中-公开
标题翻译：具有中央存储单元的处理器系统的事件信号系统和方法
公开(公告)号：WO1992005496A1
公开(公告)日：1992-04-02
申请号：PCT/US1991006713
申请日：1991-09-17
申请人： STAR SEMICONDUCTOR CORPORATION
发明人： STAR SEMICONDUCTOR CORPORATION , ROUSE, Keith , MONTLICK, Terry, F.
IPC分类号： G06F13/38
CPC分类号： G06F9/30167 , G06F13/28 , G06F15/786
摘要： An event signalling system is provided for a digital signal processor apparatus (10) which has a central data RAM (100), at least one computing processor (400), each computing processor having event occurrence circuitry, a plurality of data I/O processors (600), and a data RAM bus (125) coupled to the data RAM (100), the computing processor(s) (400) and the I/O processors (600). The event signalling system includes an address code generating circuit in each data I/O processor (600) for generating different predetermined address codes for each I/O processor (600) and for writing the predetermined address codes onto the data RAM bus (125) upon the occurrence of events of interest. The occurrence of the predetermined address codes on the data RAM bus (125) are monitored by an address decoder (196) which generates different signals depending upon the predetermined address code found. The signals from the address decoder (196) are carried by a flag bus to the event occurrence circuitry of the computing processor(s) (400) and if desired to output sections of the I/O processors (600) themselves.
摘要翻译：提供了一种用于数字信号处理器装置（10）的事件信号系统，该装置具有中央数据RAM（100），至少一个计算处理器（400），每个计算处理器具有事件发生电路，多个数据I / O处理器（600）和耦合到数据RAM（100），计算处理器（400）和I / O处理器（600）的数据RAM总线（125）。事件信号系统包括每个数据I / O处理器（600）中的地址代码产生电路，用于为每个I / O处理器（600）产生不同的预定地址代码，并将预定地址代码写入数据RAM总线（125）发生感兴趣的事件。数据RAM总线（125）上的预定地址码的发生由地址解码器（196）监视，地址解码器（196）根据找到的预定地址码产生不同的信号。来自地址解码器（196）的信号由标志总线承载到计算处理器（400）的事件发生电路，并且如果需要输出I / O处理器（600）本身的部分。

3. 发明专利

JPS59194256A Microcomputer 失效
公开(公告)号：JPS59194256A
公开(公告)日：1984-11-05
申请号：JP22145383
申请日：1983-11-26
申请人： Inmos Ltd
发明人： MAIKURU DEIBITSUDO MEI , JIYONASAN EDOWAAZU , DEIBITSUDO REONAADO UOORAA
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/46 , G06F9/48 , G06F9/52 , G06F15/78 , G06F15/80 , G11C29/00 , H01L21/761 , H01L21/822 , H01L27/04
CPC分类号： G06F9/4881 , G06F9/30167 , G06F9/30192 , G06F9/54 , G06F15/786 , G06F15/8023 , G11C29/70

4. 发明专利

JP4308144B2 Configurable processor architecture 有权
公开(公告)号：JP4308144B2
公开(公告)日：2009-08-05
申请号：JP2004552844
申请日：2003-11-11
申请人：イマジネイションテクノロジーズリミテッド
发明人：エイドリアンジョンアンダーソン , マイケルジョンディヴィス
IPC分类号： G06F9/38 , G06F9/318 , G06F15/00 , G06F15/76 , G06F15/78 , G06F15/80 , H04B1/38
CPC分类号： G06F15/786 , G06F9/3879 , G06F9/3885 , H04N5/46 , H04N21/2383 , H04N21/4382

5. 发明专利

JPS59133662A Data communication between processes in array of microcomputer and computer 失效
标题翻译： MICROCOMPUTER和计算机阵列之间的数据通信
公开(公告)号：JPS59133662A
公开(公告)日：1984-08-01
申请号：JP22145483
申请日：1983-11-26
申请人： Inmos Ltd
发明人： MAIKURU DEIBITSUDO MEI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/46 , G06F9/48 , G06F9/52 , G06F15/78 , G06F15/80 , G11C29/00 , H01L21/761 , H01L21/822 , H01L27/04
CPC分类号： G06F9/4881 , G06F9/30167 , G06F9/30192 , G06F9/54 , G06F15/786 , G06F15/8023 , G11C29/70

6. 发明申请

WO1998007099A1 A MICROCONTROLLER INCLUDING AN INTERNAL MEMORY UNIT AND CIRCUITRY TO GENERATE AN ASSOCIATED ENABLE SIGNAL 审中-公开
标题翻译：包含内部存储器的微控制器和电路产生相关的启用信号
公开(公告)号：WO1998007099A1
公开(公告)日：1998-02-19
申请号：PCT/US1997009545
申请日：1997-06-02
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , WILLIAMS, Wade, L. , SPILO, David, A. , CALVIN, Richard, T.
IPC分类号： G06F15/78
CPC分类号： G06F15/786 , G06F15/7814
摘要： A microcontroller is presented which includes a microcontroller core, an internal memory unit, an I/O pad interface unit, and several I/O pads, all formed on a single monolithic silicon substrate. The internal memory unit is configured to store data. A chip select unit within the microcontroller core generates a dedicated internal chip select (ICS#) signal which enables storage operations within the internal memory unit. Key operating parameters of the internal memory unit are stored in a single programmable internal memory chip select register (IMCSR) located within the chip select unit. The size of the internal memory unit is fixed, eliminating the need to store size information. The internal memory chip select register contains a base address field. The base address field includes a minimum number of the highest-ordered bits of a base address of the internal memory unit required to define which non-overlapping section of the physical address space the internal memory unit is mapped into. The method of accessing the internal memory unit allows backwards compatibility with existing microcontroller products. The microcontroller core also includes an execution unit and a bus interface unit. The execution unit executes microprocessor instructions, preferably instructions from an x86 instruction set. The bus interface unit handles all data transfer operations for the microcontroller core in accordance with established protocols. The I/O pad interface unit provides the microcontroller with off-chip data transfer capability, allowing the microprocessor to read data from or write data to external devices.
摘要翻译：提出了一种微控制器，其包括单个单片硅衬底上的微控制器核心，内部存储器单元，I / O焊盘接口单元和多个I / O焊盘。内部存储器单元被配置为存储数据。微控制器核心内的芯片选择单元产生专用的内部芯片选择（ICS＃）信号，其使得能够在内部存储器单元内进行存储操作。内部存储器单元的关键操作参数存储在位于芯片选择单元内的单个可编程内部存储器芯片选择寄存器（IMCSR）中。内部存储单元的大小是固定的，无需存储大小信息。内部存储器芯片选择寄存器包含一个基地址字段。基地址字段包括定义内部存储器单元被映射到的物理地址空间的哪个非重叠部分所需的内部存储器单元的基地址的最低位数。访问内部存储器单元的方法允许向后兼容现有的微控制器产品。微控制器核心还包括执行单元和总线接口单元。执行单元执行微处理器指令，优选来自x86指令集的指令。总线接口单元根据已建立的协议处理单片机内核的所有数据传输操作。 I / O接口单元为微控制器提供了片外数据传输功能，允许微处理器从外部设备读取数据或向其写入数据。

7. 发明申请

WO1991018342A1 PROGRAMMABLE SIGNAL PROCESSOR ARCHITECTURE 审中-公开
标题翻译：可编程信号处理器架构
公开(公告)号：WO1991018342A1
公开(公告)日：1991-11-28
申请号：PCT/US1991003386
申请日：1991-05-15
申请人： STAR SEMICONDUCTOR CORPORATION
发明人： STAR SEMICONDUCTOR CORPORATION , ROBINSON, Jeffrey, I. , ROUSE, Keith , MUSICUS, Bruce, R.
IPC分类号： G06F09/24
CPC分类号： G06F13/28 , G06F9/38 , G06F15/173 , G06F15/786
摘要： A programmable integrated signal processor (''SPROC'') is provided having a multiported central memory unit (RAM 100), a program memory (150), one or more digital processors (400) coupled to the RAM and to the program memory, a data flow manager (600) which controls external data flowing into the SPROC and processed data flowing out of the SPROC by acting as an interface of such data with the multiported RAM, input and output ports (700) coupled to the DFM and acting as serial interfaces for the SPROC, and a host port (800) permitting the programming of the SPROC and acting as a parallel interface to the SPROC. SPROCs may be coupled via their input and output ports to provide a system. The SPROC architecture in conjunction with a compiler and user interface system permits a user to ''sketch and realize'' complex circuits in the SPROC. An access port (900) permits reading and writing to data and program RAM memory locations. A probe (1000) permits monitoring of a memory location and provides an analog signal indicative thereof.
摘要翻译：提供了一种可编程集成信号处理器（“SPROC”），其具有多端口中央存储器单元（RAM 100），程序存储器（150），耦合到RAM和程序存储器的一个或多个数字处理器（400）数据流管理器（600），其通过充当这样的数据与多端口RAM，与DFM耦合的输入和输出端口（700）的接口来控制流入SPROC的外部数据和处理从SPROC流出的数据，并且用作 SPROC的串行接口和允许SPROC编程并作为SPROC并行接口的主机端口（800）。 SPROC可以经由其输入和输出端口耦合以提供系统。 SPROC架构与编译器和用户界面系统相结合，允许用户在SPROC中“绘制和实现”复杂的电路。访问端口（900）允许读取和写入数据和程序RAM存储器位置。探测器（1000）允许监视存储器位置并提供指示其的模拟信号。

8. 发明申请

WO2004046955A3 A CONFIGURABLE PROCESSOR ARCHITECTURE 审中-公开
标题翻译：一个可配置的处理器架构
公开(公告)号：WO2004046955A3
公开(公告)日：2005-02-10
申请号：PCT/GB0304868
申请日：2003-11-11
申请人： IMAGINATION TECH LTD
发明人： ANDERSON ADRIAN JOHN , DAVIS MICHAEL JOHN
IPC分类号： G06F9/318 , G06F9/38 , G06F15/00 , G06F15/76 , G06F15/78 , G06F15/80
CPC分类号： G06F15/786 , G06F9/3879 , G06F9/3885 , H04N5/46 , H04N21/2383 , H04N21/4382
摘要： A processor system includes a programmable very long instruction word (VLIW) processor which is closely coupled to a data memory. There is also provided a memory for storing instruction words for the VLIW processors. A memory access unit is coupled to a data memory and at least one input side is dedicated processor is coupled between a data input and the memory access unit. Furthermore, at least one output side dedicated processor is coupled between the memory access unit and the data output. The input and output side data processors perform operations common to a plurality of data processors on input and output data and the VLIW processor performs operations on data particular to a process being performed by the processor system. The VLIW processor is loaded with different sets of instruction words in dependence on the process being performed by the processor system.
摘要翻译：处理器系统包括紧密耦合到数据存储器的可编程非常长的指令字（VLIW）处理器。还提供了用于存储用于VLIW处理器的指令字的存储器。存储器访问单元耦合到数据存储器，并且至少一个输入侧是专用处理器耦合在数据输入和存储器存取单元之间。此外，至少一个输出侧专用处理器耦合在存储器访问单元和数据输出之间。输入和输出侧数据处理器对输入和输出数据上的多个数据处理器执行公共操作，并且VLIW处理器对由处理器系统执行的处理特定的数据执行操作。 VLIW处理器根据处理器系统执行的进程装入不同的指令字集合。

9. 发明申请

WO2004046955A2 A CONFIGURABLE PROCESSOR ARCHITECTURE 审中-公开
标题翻译：一个可配置的处理器架构
公开(公告)号：WO2004046955A2
公开(公告)日：2004-06-03
申请号：PCT/GB2003/004868
申请日：2003-11-11
申请人： IMAGINATION TECHNOLOGIES LIMITED
发明人： ANDERSON, Adrian, John , DAVIS, Michael, John
IPC分类号： G06F15/76
CPC分类号： G06F15/786 , G06F9/3879 , G06F9/3885 , H04N5/46 , H04N21/2383 , H04N21/4382
摘要： A processor system includes a programmable very long instruction word (VLIW) processor which is closely coupled to a data memory. There is also provided a memory for storing instruction words for the VLIW processors. A memory access unit is coupled to a data memory and at least one input side is dedicated processor is coupled between a data input and the memory access unit. Furthermore, at least one output side dedicated processor is coupled between the memory access unit and the data output. The input and output side data processors perform operations common to a plurality of data processors on input and output data and the VLIW processor performs operations on data particular to a process being performed by the processor system. The VLIW processor is loaded with different sets of instruction words in dependence on the process being performed by the processor system.
摘要翻译：处理器系统包括紧密耦合到数据存储器的可编程非常长的指令字（VLIW）处理器。还提供了用于存储用于VLIW处理器的指令字的存储器。存储器访问单元耦合到数据存储器，并且至少一个输入侧是专用处理器耦合在数据输入和存储器存取单元之间。此外，至少一个输出侧专用处理器耦合在存储器访问单元和数据输出之间。输入和输出侧数据处理器对输入和输出数据上的多个数据处理器执行公共操作，并且VLIW处理器对由处理器系统执行的处理特定的数据执行操作。 VLIW处理器根据处理器系统执行的进程装入不同的指令字集合。

10. 发明申请

WO1992004686A1 MICROCOMPUTER CIRCUIT ARRANGEMENT 审中-公开
标题翻译：微型计算机电路布置
公开(公告)号：WO1992004686A1
公开(公告)日：1992-03-19
申请号：PCT/DE1991000705
申请日：1991-09-04
申请人： SCHNEIDER, Edgar
IPC分类号： G06F15/78
CPC分类号： G06F15/786 , G06F15/7814 , G06F15/7864
摘要： A microcomputer circuit arrangement comprises a standard microprocessor or standard microcomputer (2) in the form of a monolithic integrated semi-conductor circuit, e.g. a microcomputer from the Intel 80 Cxx processor family, at least one data memory (4) in the form of a monolithic integrated semi-conductor circuit, at least one program memory (6) in the form of a monolithic integrated semi-conductor circuit, the individual monolithic semi-conductor circuits being combined in a single package (12) with external connectors (14), these connectors (14) of the single package (12) being electrically and mechanically pin compatible with a or the standard microprocessor or standard microcomputer (2) in standard package form.
摘要翻译：微计算机电路装置包括以单片集成半导体电路形式的标准微处理器或标准微型计算机（2）。来自Intel 80Cxx处理器系列的微型计算机，至少一个单片集成半导体电路形式的数据存储器（4），至少一个单体集成半导体电路形式的程序存储器（6）单个单片半导体电路被组合在具有外部连接器（14）的单个封装（12）中，单个封装（12）的这些连接器（14）在电或机械上与一个或者标准微处理器或标准微型计算机（2）标准包装形式。

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