专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5504912A Coprocessor executing pipeline control for executing protocols and instructions 失效
标题翻译：协处理器执行流水线控制以执行协议和指令
公开(公告)号：US5504912A
公开(公告)日：1996-04-02
申请号：US830460
申请日：1992-02-05
申请人： Shigeki Morinaga , Norio Nakagawa , Mitsuru Watabe , Mamoru Ohba , Hiroyuki Kida , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Shigeki Morinaga , Norio Nakagawa , Mitsuru Watabe , Mamoru Ohba , Hiroyuki Kida , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F7/00 , G06F9/38 , G06F15/16 , G06F15/167
CPC分类号： G06F9/3877 , G06F9/3885
摘要： The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.
摘要翻译：协处理器的接口部分设置有FIFO（先进先出）缓冲器和用于连续接受指令的装置。指令的流水线控制可以以这种方式进行，并且还提供了与微处理器相关联的协议装置。

2. 发明授权

US5631858A System for obtaining strict solution in accordance with accuracy of approximate solutions 失效
标题翻译：根据近似解决方案的准确度获得严格解决方案的系统
公开(公告)号：US5631858A
公开(公告)日：1997-05-20
申请号：US89103
申请日：1993-08-12
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

3. 发明授权

US5956263A Multiplication, division and square root extraction apparatus 失效
标题翻译：乘法，除法和平方根提取仪
公开(公告)号：US5956263A
公开(公告)日：1999-09-21
申请号：US797653
申请日：1997-01-31
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

4. 发明授权

US5293558A Multiplication, division and square root extraction apparatus 失效
标题翻译：乘法，除法和平方根提取仪
公开(公告)号：US5293558A
公开(公告)日：1994-03-08
申请号：US536565
申请日：1990-07-03
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： PCT No.PCT / JP89 / 01134 Sec。 371日期1990年7月3日 102（e）日期1990年7月3日PCT提交1989年11月2日PCT公布。出版物WO90 / 05335 日期1990年5月17日。一种乘法，除法和平方根提取装置，其通过使用迭代近似来计算加法，除法和平方根提取函数的解，具有连接到a的规定位宽的乘法器，加法器 - 减法器和移位器总线。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

5. 发明授权

US5125095A System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus 失效
标题翻译：在多协处理器装置中使用微处理器地址线进行协处理器选择的系统
公开(公告)号：US5125095A
公开(公告)日：1992-06-23
申请号：US678906
申请日：1991-03-28
申请人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.
摘要翻译：微计算机系统具有微处理器和多个独立的协处理器，用于根据从微处理器发送的指令数据执行各个指令。地址总线和数据总线将协处理器与微处理器互连。微处理器通过数据总线向协处理器发送指令数据，同时通过地址总线向协处理器发送协处理器指定数据。由指定数据指定的协处理器读取并对指令数据进行响应，而系统内的其他协处理器忽略指令数据。

6. 发明授权

US5642499A Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system 失效
标题翻译：用于控制处理器系统中的保存和恢复操作的执行时序的方法和装置
公开(公告)号：US5642499A
公开(公告)日：1997-06-24
申请号：US223834
申请日：1994-04-06
申请人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
发明人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F11/28 , G06F15/16 , G06F15/177
CPC分类号： G06F9/461 , G06F9/30025 , G06F9/3861 , G06F9/3885
摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.
摘要翻译：在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令的当前命令，如果当前命令是一个短命令。基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。

7. 发明授权

US5089955A Programmable counter/timer device with programmable registers having programmable functions 失效
标题翻译：具有可编程功能的可编程寄存器的可编程计数器/定时器器件
公开(公告)号：US5089955A
公开(公告)日：1992-02-18
申请号：US484909
申请日：1990-02-26
申请人： Shigeki Morinaga , Mitsuru Watabe
发明人： Shigeki Morinaga , Mitsuru Watabe
IPC分类号： G04G15/00 , G04G99/00
CPC分类号： G04G99/006 , G04G15/006
摘要： A counter timer device includes a plurality of registers each capable of performing any of the function of a counter/timer register, the function of a capture register and the function of a compare register, in accordance with a command from a central processing unit, and a plurality of task registers corresponding to tasks which are to be carried out by using the above registers. Each of the task registers stores a task instruction for specifying a counter/timer register and a capture/compare register which are used in a task, and for specifying the operation mode of each of the specified registers. The task registers are scanned to successively read out the task instructions, and each of the read-out task instructions controls the operation of each of registers used in a corresponding task. Thus, tasks corresponding to the task instructions are all carried out at once.
摘要翻译：计数器定时器装置包括多个寄存器，每个寄存器能够根据来自中央处理单元的命令执行计数器/定时器寄存器的功能，捕获寄存器的功能和比较寄存器的功能，以及对应于将通过使用上述寄存器执行的任务的多个任务寄存器。每个任务寄存器存储用于指定在任务中使用的计数器/定时器寄存器和捕获/比较寄存器的任务指令，以及用于指定每个指定寄存器的操作模式。扫描任务寄存器以连续读取任务指令，并且每个读出任务指令控制在相应任务中使用的每个寄存器的操作。因此，与任务指令相对应的任务都是一次执行的。

8. 发明授权

US5349351A Analog-digital converting device 失效
标题翻译：模拟数字转换器
公开(公告)号：US5349351A
公开(公告)日：1994-09-20
申请号：US940332
申请日：1992-09-03
申请人： Sanshiro Obara , Mitsuru Watabe , Rika Minami , Shigeki Morinaga
发明人： Sanshiro Obara , Mitsuru Watabe , Rika Minami , Shigeki Morinaga
IPC分类号： G01R19/00 , G06F15/78 , H02M7/48 , H03M1/12 , G05B11/28
CPC分类号： H03M1/1225
摘要： An analog-digital converting device is designed such that when an operation of converting a special analog signal into a digital signal and an operation of converting another analog signal into a digital signal are instructed concurrently, priority is given to the conversion operation of the special analog signal, The analog-digital converting device includes an analog multiplexer having a main channel and a sub channel, a sample holder, an AD converter, a conversion result register having a plurality of storage areas, and an AD control circuit for controlling the drive of the individual components according to an instruction of a CPU. When the analog signals input to the channels are converted into digital signals in sequence, priority is given to AD conversion of the analog signal input to the main channel over AD conversion of the analog signal input to the sub channel.
摘要翻译：模拟数字转换装置被设计成当同时指示将特殊模拟信号转换为数字信号的操作和将另一个模拟信号转换为数字信号的操作时，优先考虑特殊模拟信号的转换操作模拟数字转换装置包括具有主信道和子信道的模拟多路复用器，样本保持器，AD转换器，具有多个存储区域的转换结果寄存器，以及用于控制驱动器的AD控制电路各个组件根据CPU的指令。当输入到通道的模拟信号按顺序转换为数字信号时，通过AD转换将模拟信号输入到主通道的模拟信号的AD转换优先给输入到子通道。

9. 发明授权

US4621224A Position/speed detection method and apparatus 失效
标题翻译：位置/速度检测方法和装置
公开(公告)号：US4621224A
公开(公告)日：1986-11-04
申请号：US721959
申请日：1985-04-11
申请人： Mitsuru Watabe , Shigeki Morinaga , Yasuyuki Sugiura , Tadashi Takahashi
发明人： Mitsuru Watabe , Shigeki Morinaga , Yasuyuki Sugiura , Tadashi Takahashi
IPC分类号： G01D5/245 , G01D5/244 , G01P3/42 , G01P3/489 , G05B11/18
CPC分类号： G01P3/489
摘要： A position/speed detection method and apparatus employing an encoder mounted on the rotary shaft of a motor in order to control the position and speed, wherein the coarse position and fine position are simultaneously detected by an encoder pulse and an encoder original signal, respectively and the detected results are combined to detect the position and speed of the motor with high precision.
摘要翻译：一种位置/速度检测方法和装置，其使用安装在电机的旋转轴上的编码器来控制位置和速度，其中粗略位置和精细位置分别由编码器脉冲和编码器原始信号同时检测，结合检测结果，高精度地检测电机的位置和速度。

10. 发明授权

US4922175A Position/speed detection method and apparatus 失效
标题翻译：位置/速度检测方法和装置
公开(公告)号：US4922175A
公开(公告)日：1990-05-01
申请号：US318688
申请日：1989-03-03
申请人： Yasuyuki Sugiura , Mitsuru Watabe , Shigeki Morinaga , Kunio Miyashita , Hiroshi Sugai
发明人： Yasuyuki Sugiura , Mitsuru Watabe , Shigeki Morinaga , Kunio Miyashita , Hiroshi Sugai
IPC分类号： G01D5/245 , G01D5/244
CPC分类号： G01D5/24409
摘要： Disclosed is a position detecting method and apparatus which are suitable for detecting the position of a moving body on the basis of the output of a position detector for generating two-phase periodic waves having a phase difference of a quarter period, the method comprising the steps of: comparing either one of the two-phase periodic waves with a predetermined reference value having hysteresis to thereby obtain a roughly estimated position for every half period of the one periodic wave; analog-to-digital converting the two-phase periodic waves and a zero-cross value for every sampling period to thereby obtain a finely estimated position; and detecting the position of the moving body on the basis of the roughly estimated position and the finely estimated position while correcting an error due to the hysteresis at the starting point of the roughly estimated position, by use of the relationship between the roughly estimated position and the finely estimated position. According to this method/apparatus, continuity between the roughly estimated position and the finely estimated position can be maintained, so that exact and high-resolution position detection can be performed.
摘要翻译：公开了一种位置检测方法和装置，其适用于根据用于产生具有四分之一周期的相位差的两相周期波的位置检测器的输出来检测移动体的位置，该方法包括步骤：将两相周期波中的任一个与具有滞后的预定参考值进行比较，从而获得一个周期波的每半个周期的粗略估计位置; 在每个采样周期对模拟数字转换两相周期波和零交叉值，从而获得精细估计的位置; 并且通过使用粗略估计位置与粗略估计位置之间的关系，在粗略估计位置和精确估计位置的基础上检测移动体的位置，同时校正由于在粗略估计位置的起点处的滞后导致的误差精细估计的位置。根据该方法/装置，能够维持粗略估计位置与精细估计位置之间的连续性，从而能够进行精确，高分辨率的位置检测。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式