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1. 发明授权

US07721123B2 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US07721123B2
公开(公告)日：2010-05-18
申请号：US12025649
申请日：2008-02-04
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

2. 发明申请

US20080126817A1 METHOD AND APPARATUS FOR MANAGING THE POWER CONSUMPTION OF A DATA PROCESSING SYSTEM 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US20080126817A1
公开(公告)日：2008-05-29
申请号：US12025649
申请日：2008-02-04
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

3. 发明授权

US07356713B2 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US07356713B2
公开(公告)日：2008-04-08
申请号：US10631537
申请日：2003-07-31
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops.
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式。

4. 发明授权

US07062612B2 Updating remote locked cache 失效
标题翻译：更新远程锁定缓存
公开(公告)号：US07062612B2
公开(公告)日：2006-06-13
申请号：US10318594
申请日：2002-12-12
申请人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
发明人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry in the cache. Upon determining that the snoop request has a valid entry in the cache, the data is caught and sent to the cache for update.
摘要翻译：提供了一种用于直接访问数据缓存的系统和方法。数据传输请求被发送到系统总线，用于将数据传送到系统存储器。数据传输请求被窥探。侦听请求被发送到缓存。确定窥探请求是否在高速缓存中具有有效的条目。在确定窥探请求在缓存中具有有效条目时，数据被捕获并发送到缓存以供更新。

5. 发明授权

US07299372B2 Hierarchical management for multiprocessor system with real-time attributes 失效
标题翻译：具有实时属性的多处理器系统的分层管理
公开(公告)号：US07299372B2
公开(公告)日：2007-11-20
申请号：US10912481
申请日：2004-08-05
申请人： Jeffrey Douglas Brown , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , Michael Fan Wang
发明人： Jeffrey Douglas Brown , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , Michael Fan Wang
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译：本发明提供用于控制元件的功耗。第一个功率控制命令由该元件的软件发出。确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

6. 发明授权

US07107363B2 Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
标题翻译：具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法
公开(公告)号：US07107363B2
公开(公告)日：2006-09-12
申请号：US10464882
申请日：2003-06-19
申请人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
发明人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F3/00
CPC分类号： G06F9/5011 , G06F2209/5014
摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.
摘要翻译：本发明在一个方面公开了一种微处理器。在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。还公开了一种协调带宽分配的方法和处理器组件。

7. 发明授权

US07099975B2 Method of resource arbitration 失效
标题翻译：资源仲裁方法
公开(公告)号：US07099975B2
公开(公告)日：2006-08-29
申请号：US10730952
申请日：2003-12-09
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns , Takeshi Yamazaki
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F13/3625
摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.
摘要翻译：一种改进的资源仲裁方法和装置。定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。优先级分配给每个资源访问请求。为每个资源创建访问请求集中器（ARC），通过该资源访问资源。在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

8. 发明授权

US07818507B2 Methods and apparatus for facilitating coherency management in distributed multi-processor system 有权
标题翻译：用于促进分布式多处理器系统中的一致性管理的方法和装置
公开(公告)号：US07818507B2
公开(公告)日：2010-10-19
申请号：US11098621
申请日：2005-04-04
申请人： Takeshi Yamazaki , Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns
发明人： Takeshi Yamazaki , Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要翻译：方法和装置提供从多个设备中的第一设备向多个处理系统中的第一个内的第一地址集中器发送数据命令; 选择其他处理系统之一，所选择的处理系统具有由其中存储的数据命令寻址的数据; 将所述数据命令发送到所选择的处理系统的第一地址集中器; 以及从所选择的处理系统的第一地址集中器将数据命令广播到每个处理系统中的第二地址集中器。

9. 发明授权

US08112590B2 Methods and apparatus for reducing command processing latency while maintaining coherence 失效
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

10. 发明授权

US07836258B2 Dynamic data cache invalidate with data dependent expiration 有权
标题翻译：动态数据缓存无效，与数据相关的到期
公开(公告)号：US07836258B2
公开(公告)日：2010-11-16
申请号：US11559090
申请日：2006-11-13
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F12/0808 , G06F12/1045 , G06T1/60
摘要： According to embodiments of the invention, a distributed time base signal may be coupled to a memory directory which provides address translation for data located within a memory cache. The memory directory may have attribute bits which indicate whether or not the memory entries have been accessed by the distributed time base signal. Furthermore, the memory directory may have attribute bits which indicate whether or not a memory directory entry should be considered invalid after an access to the memory entry by the distributed time base signal. If the memory directory entry has been accessed by the distributed time base signal and the memory directory entry should be considered invalid after the access by the time base signal, any attempted address translation using the memory directory entry may cause a cache miss. The cache miss may initiate the retrieval of valid data from memory.
摘要翻译：根据本发明的实施例，分布式时基信号可以耦合到为位于存储器高速缓存内的数据提供地址转换的存储器目录。存储器目录可以具有指示存储器条目是否已经被分布式时基信号访问的属性位。此外，存储器目录可以具有指示在通过分布式时基信号访问存储器条目之后存储目录条目是否应被视为无效的属性位。如果通过分布式时基信号访问存储器目录条目，并且在通过时基信号访问之后，存储器目录条目应被视为无效，则使用存储器目录条目的任何尝试的地址转换可能导致高速缓存未命中。高速缓存未命中可以启动从存储器检索有效数据。

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