专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07099975B2 Method of resource arbitration 失效
标题翻译：资源仲裁方法
公开(公告)号：US07099975B2
公开(公告)日：2006-08-29
申请号：US10730952
申请日：2003-12-09
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns , Takeshi Yamazaki
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F13/3625
摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.
摘要翻译：一种改进的资源仲裁方法和装置。定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。优先级分配给每个资源访问请求。为每个资源创建访问请求集中器（ARC），通过该资源访问资源。在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

2. 发明授权

US07818507B2 Methods and apparatus for facilitating coherency management in distributed multi-processor system 有权
标题翻译：用于促进分布式多处理器系统中的一致性管理的方法和装置
公开(公告)号：US07818507B2
公开(公告)日：2010-10-19
申请号：US11098621
申请日：2005-04-04
申请人： Takeshi Yamazaki , Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns
发明人： Takeshi Yamazaki , Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要翻译：方法和装置提供从多个设备中的第一设备向多个处理系统中的第一个内的第一地址集中器发送数据命令; 选择其他处理系统之一，所选择的处理系统具有由其中存储的数据命令寻址的数据; 将所述数据命令发送到所选择的处理系统的第一地址集中器; 以及从所选择的处理系统的第一地址集中器将数据命令广播到每个处理系统中的第二地址集中器。

3. 发明授权

US08112590B2 Methods and apparatus for reducing command processing latency while maintaining coherence 失效
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

4. 发明授权

US07802023B2 Methods and apparatus for supporting multiple configurations in a multi-processor system 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US07802023B2
公开(公告)日：2010-09-21
申请号：US11250246
申请日：2005-10-14
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F13/42
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

5. 发明授权

US08010716B2 Methods and apparatus for supporting multiple configurations in a multi-processor system 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US08010716B2
公开(公告)日：2011-08-30
申请号：US12858915
申请日：2010-08-18
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

6. 发明申请

US20100312969A1 Methods And Apparatus For Supporting Multiple Configurations In A Multi-Processor System 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US20100312969A1
公开(公告)日：2010-12-09
申请号：US12858915
申请日：2010-08-18
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

7. 发明授权

US07107363B2 Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
标题翻译：具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法
公开(公告)号：US07107363B2
公开(公告)日：2006-09-12
申请号：US10464882
申请日：2003-06-19
申请人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
发明人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F3/00
CPC分类号： G06F9/5011 , G06F2209/5014
摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.
摘要翻译：本发明在一个方面公开了一种微处理器。在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。还公开了一种协调带宽分配的方法和处理器组件。

8. 发明授权

US07975064B2 Envelope packet architecture for broadband engine 有权
标题翻译：宽带引擎的信封包架构
公开(公告)号：US07975064B2
公开(公告)日：2011-07-05
申请号：US10942422
申请日：2004-09-16
申请人： Michael Joseph Carnevale , Scott Douglas Clark , David Wayne Hill , Charles Ray Johns , Thomas K. Pokrandt , Jeffrey Joseph Ruedinger , Dorothy Marie Thelen
发明人： Michael Joseph Carnevale , Scott Douglas Clark , David Wayne Hill , Charles Ray Johns , Thomas K. Pokrandt , Jeffrey Joseph Ruedinger , Dorothy Marie Thelen
IPC分类号： G06F15/16
CPC分类号： H04L1/188
摘要： A mechanism provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.
摘要翻译：一种机制用于发送信封并回复信封。发射机被配置为发送信封。接收机耦合到发射机，其中接收机被配置为接收信封并产生回复信封。发送缓冲器耦合到发送器。接收缓冲器耦合到接收器。重试定时器耦合到发射机，其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络，则发射机被配置为重发信封。这导致从发射机和接收机两者发送的信封总数的减少。

9. 发明授权

US07669013B2 Directory for multi-node coherent bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US07669013B2
公开(公告)日：2010-02-23
申请号：US11828439
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。如果本地节点确定请求是本地请求，则执行本地节点目录的查找。如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。否则，请求将转发到多节点系统中的所有远程节点。

10. 发明申请

US20090031086A1 Directory For Multi-Node Coherent Bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US20090031086A1
公开(公告)日：2009-01-29
申请号：US11828448
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/16
CPC分类号： G06F12/0822
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。本地节点确定请求是本地还是系统请求。如果请求是本地请求，则执行本地节点中的目录的查找。如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输如果需要，请求中指定的数据将被执行，并且请求是本地请求。如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式