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1. 发明授权

US08483227B2 Controlling bandwidth reservations method and apparatus 有权
标题翻译：控制带宽预留方法和装置
公开(公告)号：US08483227B2
公开(公告)日：2013-07-09
申请号：US10718302
申请日：2003-11-20
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： H04L12/56
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

2. 发明申请

US20110246695A1 CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS 失效
标题翻译：控制带宽预留方法和装置
公开(公告)号：US20110246695A1
公开(公告)日：2011-10-06
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： G06F12/00
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

3. 发明授权

US08611368B2 Controlling bandwidth reservations method and apparatus 失效
公开(公告)号：US08611368B2
公开(公告)日：2013-12-17
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： H04L12/43 , H04L12/28
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

4. 发明申请

US20090077322A1 System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus 审中-公开
标题翻译：通过BEB总线通过仅数据传输协议向Getllar命中缓存行数据转发的系统和方法
公开(公告)号：US20090077322A1
公开(公告)日：2009-03-19
申请号：US11857674
申请日：2007-09-19
申请人： Charles Ray Johns , Roy Moonseuk Kim , Peichun Peter Liu , Shigehiro Asano , Anushkumar Rengarajan
发明人： Charles Ray Johns , Roy Moonseuk Kim , Peichun Peter Liu , Shigehiro Asano , Anushkumar Rengarajan
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1016
摘要： A system and method for using a data-only transfer protocol to store atomic cache line data in a local storage area is presented. A processing engine includes an atomic cache and a local storage. When the processing engine encounters a request to transfer cache line data from the atomic cache to the local storage (e.g., GETTLAR command), the processing engine utilizes a data-only transfer protocol to pass cache line data through the external bus node and back to the processing engine. The data-only transfer protocol comprises a data phase and does not include a prior command phase or snoop phase due to the fact that the processing engine communicates to the bus node instead of an entire computer system when the processing engine sends a data request to transfer data to itself.
摘要翻译：提出了一种使用仅数据传输协议将原始高速缓存行数据存储在本地存储区域中的系统和方法。处理引擎包括原子缓存和本地存储。当处理引擎遇到将高速缓存行数据从原子缓存传送到本地存储器（例如，GETTLAR命令）的请求时，处理引擎利用仅数据传输协议通过外部总线节点传递高速缓存行数据并返回处理引擎。仅数据传输协议包括数据相位，并且不包括先前的命令阶段或窥探阶段，因为当处理引擎发送数据请求传送时处理引擎与总线节点而不是整个计算机系统通信数据本身。

5. 发明授权

US07107376B2 Systems and methods for bandwidth shaping 有权
标题翻译：带宽整形的系统和方法
公开(公告)号：US07107376B2
公开(公告)日：2006-09-12
申请号：US10764626
申请日：2004-01-26
申请人： Shigehiro Asano , Peichun Peter Liu , David Mui
发明人： Shigehiro Asano , Peichun Peter Liu , David Mui
IPC分类号： G06F13/362 , G06F13/372
CPC分类号： G06F13/3625
摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.
摘要翻译：用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。整形监视器根据其相对优先级向处理器分配插槽。首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。

6. 发明申请

US20050111354A1 Controlling bandwidth reservations method and apparatus 有权
标题翻译：控制带宽预留方法和装置
公开(公告)号：US20050111354A1
公开(公告)日：2005-05-26
申请号：US10718302
申请日：2003-11-20
申请人： Shigehiro Asano , Charles Johns , Matthew King , Peichun Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Johns , Matthew King , Peichun Liu , David Mui , Jieming Qi
IPC分类号： H04L12/24 , H04L12/26
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

7. 发明授权

US07721123B2 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US07721123B2
公开(公告)日：2010-05-18
申请号：US12025649
申请日：2008-02-04
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

8. 发明授权

US07233998B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07233998B2
公开(公告)日：2007-06-19
申请号：US09816004
申请日：2001-03-22
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

9. 发明申请

US20080126817A1 METHOD AND APPARATUS FOR MANAGING THE POWER CONSUMPTION OF A DATA PROCESSING SYSTEM 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US20080126817A1
公开(公告)日：2008-05-29
申请号：US12025649
申请日：2008-02-04
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

10. 发明授权

US07356713B2 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US07356713B2
公开(公告)日：2008-04-08
申请号：US10631537
申请日：2003-07-31
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops.
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式。

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