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1. 发明授权

US08536011B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US08536011B2
公开(公告)日：2013-09-17
申请号：US13074836
申请日：2011-03-29
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/336 , H01L21/44 , H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

2. 发明授权

US07939440B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US07939440B2
公开(公告)日：2011-05-10
申请号：US11152375
申请日：2005-06-15
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/425 , H01L21/44
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

3. 发明授权

US08912014B1 Controlling the latchup effect 有权
标题翻译：控制闭锁效果
公开(公告)号：US08912014B1
公开(公告)日：2014-12-16
申请号：US11333208
申请日：2006-01-18
申请人： Chuan Lin , Dong-Hyuk Ju , Imran Khan , Jun Kang , Shibly S. Ahmed
发明人： Chuan Lin , Dong-Hyuk Ju , Imran Khan , Jun Kang , Shibly S. Ahmed
IPC分类号： H01L21/66
CPC分类号： G01R31/27 , G01R31/2884 , H01L22/12 , H01L22/34 , H01L27/0921
摘要： A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.
摘要翻译：一种方法包括在源极区域或漏极区域中的至少一个与阱接触区域之间改变间隔以产生一组构型。该方法还包括确定闭锁对每个配置的影响。

4. 发明授权

US07179692B2 Method of manufacturing a semiconductor device having a fin structure 有权
标题翻译：具有翅片结构的半导体器件的制造方法
公开(公告)号：US07179692B2
公开(公告)日：2007-02-20
申请号：US10913409
申请日：2004-08-09
申请人： Bin Yu , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
发明人： Bin Yu , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/42384 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.
摘要翻译：形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。

5. 发明授权

US07095065B2 Varying carrier mobility in semiconductor devices to achieve overall design goals 有权
标题翻译：在半导体器件中改变载波的移动性，实现总体设计目标
公开(公告)号：US07095065B2
公开(公告)日：2006-08-22
申请号：US10633504
申请日：2003-08-05
申请人： Bin Yu , Shibly S. Ahmed , Haihong Wang
发明人： Bin Yu , Shibly S. Ahmed , Haihong Wang
IPC分类号： H01L29/80
CPC分类号： H01L29/785 , H01L27/1203 , H01L29/42392 , H01L29/66795
摘要： A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.
摘要翻译：半导体器件可以包括衬底和形成在衬底上的绝缘层。第一器件可以形成在绝缘层上，包括第一鳍片。第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。第二装置可以形成在绝缘层上，包括第二鳍片。第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

6. 发明授权

US08217450B1 Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin 有权
标题翻译：双栅半导体器件，其栅极触点形成在翅片的相邻侧壁处
公开(公告)号：US08217450B1
公开(公告)日：2012-07-10
申请号：US10770011
申请日：2004-02-03
申请人： Bin Yu , Shibly S. Ahmed , Haihong Wang
发明人： Bin Yu , Shibly S. Ahmed , Haihong Wang
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/7855 , H01L29/7856
摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is adjacent a first sidewall of the fin. The second gate is formed on the insulating layer and is adjacent a second sidewall of the fin opposite the first sidewall. The first and second gates both include a conductive material and are electrically separated by the fin.
摘要翻译：双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。绝缘层形成在基板上，并且鳍形成在绝缘层上。第一栅极形成在绝缘层上并与鳍片的第一侧壁相邻。第二栅极形成在绝缘层上并且与第一侧壁相对的翅片的第二侧壁相邻。第一和第二栅极都包括导电材料并且被散热片电隔离。

7. 发明授权

US06998301B1 Method for forming a tri-gate MOSFET 失效
标题翻译：形成三栅极MOSFET的方法
公开(公告)号：US06998301B1
公开(公告)日：2006-02-14
申请号：US10653225
申请日：2003-09-03
申请人： Bin Yu , Shibly S. Ahmed
发明人： Bin Yu , Shibly S. Ahmed
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/02672 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/2022 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method for forming a tri-gate semiconductor device that includes a substrate and a dielectric layer formed on the substrate includes depositing a first dielectric layer on the dielectric layer and etching the first dielectric layer to form a structure. The method further includes depositing a second dielectric layer over the structure, depositing an amorphous silicon layer over the second dielectric layer, etching the amorphous silicon layer to form amorphous silicon spacers, where the amorphous silicon spacers are disposed on opposite sides of the structure, depositing a metal layer on at least an upper surface of each of the amorphous silicon spacers, annealing the metal layer to convert the amorphous silicon spacers to crystalline silicon fin structures, removing a portion of the second dielectric layer, depositing a gate material, and etching the gate material to form three gates.
摘要翻译：一种形成三栅极半导体器件的方法，包括在衬底上形成的衬底和电介质层，包括在电介质层上沉积第一介电层并蚀刻第一介电层以形成结构。该方法还包括在结构上沉积第二介电层，在第二介电层上沉积非晶硅层，蚀刻非晶硅层以形成非晶硅间隔物，其中非晶硅间隔物设置在结构的相对侧上，沉积在每个非晶硅间隔物的至少上表面上的金属层，退火金属层以将非晶硅间隔物转化为晶体硅鳍结构，去除第二电介质层的一部分，沉积栅极材料，并蚀刻门材料形成三门。

8. 发明授权

US06958512B1 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US06958512B1
公开(公告)日：2005-10-25
申请号：US10770010
申请日：2004-02-03
申请人： Yider Wu , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Yider Wu , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/788
CPC分类号： H01L29/42324 , H01L29/66795 , H01L29/785 , H01L29/7881
摘要： A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.
摘要翻译：非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。导电结构可以用作非易失性存储器件的浮栅电极。

9. 发明授权

US06812119B1 Narrow fins by oxidation in double-gate finfet 有权
标题翻译：狭窄的翅片通过氧化在双门finfet
公开(公告)号：US06812119B1
公开(公告)日：2004-11-02
申请号：US10614052
申请日：2003-07-08
申请人： Shibly S. Ahmed , Ming-Ren Lin , Haihong Wang , Bin Yu
发明人： Shibly S. Ahmed , Ming-Ren Lin , Haihong Wang , Bin Yu
IPC分类号： H01L213205
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
摘要翻译：一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。该方法还包括在每个双盖的侧面上形成间隔物，并在双重帽下面的第一半导体材料层中形成双翅片。该方法还包括使双翅片变薄以产生窄的双翅片。

10. 发明授权

US06787406B1 Systems and methods for forming dense n-channel and p-channel fins using shadow implanting 有权
标题翻译：使用阴影植入形成致密的n通道和p通道翅片的系统和方法
公开(公告)号：US06787406B1
公开(公告)日：2004-09-07
申请号：US10638334
申请日：2003-08-12
申请人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/66803 , Y10S438/944
摘要： A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.
摘要翻译：一种方法有助于掺杂包括衬底的半导体器件的散热片。该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

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