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1. 发明授权

US6133147A Process for selective metal deposition in holes of semiconductor device 失效
标题翻译：在半导体器件的孔中选择性金属沉积的工艺
公开(公告)号：US6133147A
公开(公告)日：2000-10-17
申请号：US139701
申请日：1998-08-25
申请人： Shi-Woo Rhee , Jong-Ho Yun
发明人： Shi-Woo Rhee , Jong-Ho Yun
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44 , B05D5/12
CPC分类号： H01L21/76879
摘要： A process for preparing a metallic interconnecting plug in a semiconductor device which comprises the steps of: i) forming an insulating layer on the surface of a semiconductor substrate or a metal underlayer of the semiconductor device, ii) forming a hole in the insulating layer to expose the surface of the semiconductor substrate or the metal underlayer, iii) exposing the surface of the insulating layer to the vapor of a blocking agent under a pressure ranging from 10.sup.-12 to 10 torr for a controlled time period so that a blocking layer is formed only on the outer surface of the insulating layer, the blocking layer not extending over the inside walls of the hole, iv) selectively depositing a conductive metal in the hole using a chemical vapor deposition method to form the metallic interconnecting plug which extends from the surface of the semiconductor substrate or the metal underlayer to the level of the outer surface of the insulating layer, and v) removing the blocking layer from the surface of the insulating layer.
摘要翻译：一种在半导体器件中制备金属互连插头的方法，包括以下步骤：i）在半导体器件的半导体衬底或金属底层的表面上形成绝缘层，ii）在绝缘层中形成孔，暴露半导体衬底或金属底层的表面，iii）在10-12至10托的压力下将绝缘层的表面暴露于封闭剂的蒸气一段受控的时间段内，使得阻挡层为仅形成在绝缘层的外表面上，阻挡层不延伸到孔的内壁上，iv）使用化学气相沉积法选择性地在孔中沉积导电金属，以形成金属互连插塞，其从半导体衬底或金属底层的表面到绝缘层的外表面的水平面，以及v）从第二绝缘层去除阻挡层 e表面的绝缘层。

2. 发明申请

US20080211038A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080211038A1
公开(公告)日：2008-09-04
申请号：US11965420
申请日：2007-12-27
申请人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
发明人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。初步栅极图案包括栅极氧化物图案，导电图案和牺牲绝缘图案。该方法还包括在初步栅极图案的相对侧壁上形成间隔物，形成层间电介质图案以暴露牺牲绝缘图案，去除牺牲绝缘图案以形成露出导电图案的开口，将导电图案转变为金属硅化物并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。金属硅化物层和金属导电图案构成栅电极。

3. 发明授权

US07416968B2 Methods of forming field effect transistors having metal silicide gate electrodes 有权
标题翻译：形成具有金属硅化物栅电极的场效应晶体管的方法
公开(公告)号：US07416968B2
公开(公告)日：2008-08-26
申请号：US11230586
申请日：2005-09-20
申请人： Hyun-Su Kim , Jong-Ho Yun , Byung-Hak Lee , Eun-Ji Jung , Gil-Heyun Choi
发明人： Hyun-Su Kim , Jong-Ho Yun , Byung-Hak Lee , Eun-Ji Jung , Gil-Heyun Choi
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This first metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The first metal layer and the conductive gate electrode are thermally treated for a sufficient duration to convert a first portion of the conductive gate electrode into a first metal silicide region. The first metal layer and the first metal silicide region are then removed to expose a second portion of the conductive gate electrode. A second metal layer is then formed on the second portion of the conductive gate electrode. This second metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The second metal layer and the second portion of the conductive gate electrode are thermally treated for a sufficient duration to thereby convert the second portion of the conductive gate electrode into a second metal silicide region.
摘要翻译：根据本发明的实施例的形成场效应晶体管的方法包括在半导体衬底上形成导电栅电极（例如，多晶硅栅电极），并在导电栅电极上形成第一金属层。该第一金属层可以包括选自镍，钴，钛，钽和钨的材料。对第一金属层和导电栅电极进行热处理足够的时间以将导电栅电极的第一部分转换成第一金属硅化物区域。然后去除第一金属层和第一金属硅化物区域以暴露导电栅电极的第二部分。然后在导电栅电极的第二部分上形成第二金属层。该第二金属层可以包括选自镍，钴，钛，钽和钨的材料。第二金属层和导电栅电极的第二部分被热处理足够的持续时间，从而将导电栅电极的第二部分转换成第二金属硅化物区域。

4. 发明申请

US20080199991A1 STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 有权
标题翻译：堆叠半导体器件和制造方法
公开(公告)号：US20080199991A1
公开(公告)日：2008-08-21
申请号：US12108591
申请日：2008-04-24
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.
摘要翻译：叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜形成在上层晶体管上的较低层间绝缘膜上。叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

5. 发明申请

US20080124921A1 METHOD FORMING OHMIC CONTACT LAYER AND METAL WIRING IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成OHMIC接触层和金属接线的方法
公开(公告)号：US20080124921A1
公开(公告)日：2008-05-29
申请号：US11772953
申请日：2007-07-03
申请人： Dae-Yong Kim , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Dae-Yong Kim , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/28518 , H01L21/76843 , H01L21/76855
摘要： A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.
摘要翻译：一种形成欧姆接触层的方法，包括在基板上形成绝缘层图案，所述绝缘图案层具有选择性地暴露含硅层的开口，使用无电极电镀工艺在暴露的硅轴承层上形成金属层，以及使用硅化法从所述硅轴承层和所述金属层形成金属硅化物层。另外，使用上述形成欧姆接触层的方法在半导体器件中形成金属布线的方法。

6. 发明授权

US07867898B2 Method forming ohmic contact layer and metal wiring in semiconductor device 有权
标题翻译：在半导体器件中形成欧姆接触层和金属布线的方法
公开(公告)号：US07867898B2
公开(公告)日：2011-01-11
申请号：US11772953
申请日：2007-07-03
申请人： Dae-Yong Kim , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Dae-Yong Kim , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76843 , H01L21/76855
摘要： A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.
摘要翻译：一种形成欧姆接触层的方法，包括在基板上形成绝缘层图案，所述绝缘图案层具有选择性地暴露含硅层的开口，使用无电极电镀工艺在暴露的硅轴承层上形成金属层，以及使用硅化法从所述硅轴承层和所述金属层形成金属硅化物层。另外，使用上述形成欧姆接触层的方法在半导体器件中形成金属布线的方法。

7. 发明授权

US07846796B2 Semiconductor devices including buried bit lines 有权
标题翻译：半导体器件包括埋地位线
公开(公告)号：US07846796B2
公开(公告)日：2010-12-07
申请号：US12791692
申请日：2010-06-01
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other
摘要翻译：半导体器件包括半导体衬底上的多个沟道结构。具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

8. 发明授权

US07833847B2 Method of forming semiconductor device having stacked transistors 有权
标题翻译：形成具有堆叠晶体管的半导体器件的方法
公开(公告)号：US07833847B2
公开(公告)日：2010-11-16
申请号：US12503556
申请日：2009-07-15
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/84 , H01L21/00 , H01L21/44 , H01L21/4763 , H01L21/762
CPC分类号： H01L21/28518 , H01L21/76898 , H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1108
摘要： There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.
摘要翻译：提供了一种形成具有堆叠晶体管的半导体器件的方法。当形成用于将堆叠的晶体管彼此连接的接触孔时，共同接触孔的底部和侧壁上的欧姆层分开形成。结果，各个欧姆层被最佳地形成以满足要求或条件。因此，公共接点的接触电阻可以最小化，从而可以提高半导体器件的速度。

9. 发明授权

US07662707B2 Method of forming relatively continuous silicide layers for semiconductor devices 失效
标题翻译：形成半导体器件相对连续的硅化物层的方法
公开(公告)号：US07662707B2
公开(公告)日：2010-02-16
申请号：US11247770
申请日：2005-10-11
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung
IPC分类号： H01L21/28 , H01L21/44 , H01L21/4763
CPC分类号： H01L29/78 , H01L29/665 , H01L29/66515
摘要： Methods of forming metal silicide layers in a semiconductor device are provided in which a first metal silicide layer may be formed on a substrate, where the first metal silicide layer comprises a plurality of fragments of a metal silicide that are separated by one or more gaps. A conductive material is selectively deposited into at least some of the gaps in the first metal silicide layer in order to electrically connect at least some of the plurality of fragments.
摘要翻译：提供了在半导体器件中形成金属硅化物层的方法，其中可以在衬底上形成第一金属硅化物层，其中第一金属硅化物层包括由一个或多个间隙分开的多个金属硅化物片段。导电材料被选择性沉积到第一金属硅化物层中的至少一些间隙中，以电连接多个片段中的至少一些。

10. 发明授权

US07435634B2 Methods of forming semiconductor devices having stacked transistors 失效
标题翻译：形成具有层叠晶体管的半导体器件的方法
公开(公告)号：US07435634B2
公开(公告)日：2008-10-14
申请号：US11398192
申请日：2006-04-05
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/84
CPC分类号： H01L21/8221 , H01L21/28518 , H01L21/76829 , H01L21/76898 , H01L27/0688 , Y10S257/903
摘要： A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成层间绝缘层，并且层间绝缘层可以具有暴露半导体衬底的一部分的接触孔。可以在接触孔中和在与半导体衬底相对的接触孔附近的层间绝缘层的部分上形成单晶半导体插塞，并且与半导体衬底相对的部分层间绝缘层可以不含单晶半导体插头。可以去除接触孔中的单晶半导体插塞的部分，同时将单晶半导体插塞的部分保持在与接触孔相邻的层间绝缘层的部分上作为单晶半导体接触图案。在去除单晶半导体插头的部分之后，可以在层间绝缘层和单晶半导体接触图案上形成单晶半导体层。可以在单晶半导体层上形成第二层间绝缘层，并且可以通过单晶半导体层通过第二层间绝缘层形成公共接触孔，并且通过第一层间绝缘层暴露半导体的一部分基质。此外，可以在与半导体衬底接触的公共接触孔中形成导电接触插塞。还讨论了相关设备。

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