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1. 发明授权

US07256429B2 Memory cell with buffered-layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US07256429B2
公开(公告)日：2007-08-14
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

2. 发明授权

US07141481B2 Method of fabricating nano-scale resistance cross-point memory array 有权
标题翻译：制造纳米级电阻交叉点存储阵列的方法
公开(公告)号：US07141481B2
公开(公告)日：2006-11-28
申请号：US10909218
申请日：2004-07-29
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L21/20
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

3. 发明授权

US06911361B2 Low temperature processing of PCMO thin film on Ir substrate for RRAM application 有权
标题翻译：用于RRAM应用的Ir衬底上的PCMO薄膜的低温处理
公开(公告)号：US06911361B2
公开(公告)日：2005-06-28
申请号：US10384846
申请日：2003-03-10
申请人： Fengyan Zhang , Wei-Wei Zhuang , Wei Pan , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Wei Pan , Sheng Teng Hsu
IPC分类号： H01L27/108 , G11C13/00 , H01L45/00 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.
摘要翻译：在用于RRAM器件的铱衬底上施加PCMO薄膜的方法包括制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积一层铱; 在铱上旋涂一层PCMO; 在三步烘烤过程中烘烤PCMO和基材; 在RTP室中对基板和PCMO进行后烘烤退火; 重复所述旋涂，烘烤和退火步骤直到PCMO具有所需的厚度; 退火基板和PCMO; 沉积顶部电极; 并完成RRAM设备。

4. 发明授权

US06887523B2 Method for metal oxide thin film deposition via MOCVD 有权
标题翻译：通过MOCVD沉积金属氧化物薄膜的方法
公开(公告)号：US06887523B2
公开(公告)日：2005-05-03
申请号：US10326347
申请日：2002-12-20
申请人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan
IPC分类号： H01L21/205 , C23C16/40 , H01L21/316 , H01L27/10 , H01L45/00
CPC分类号： G11C13/0007 , C23C16/40 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： An MOCVD process is provided for forming metal-containing films having the general formula M′xM″(1−x)MyOz, wherein M′ is a metal selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, and Gd; M″ is a metal selected from the group consisting of Mg, Ca, Sr, Ba, Pb, Zn, and Cd; M is a metal selected from the group consisting of Mn, Ce, V, Fe, Co, Nb, Ta, Cr, Mo, W, Zr, Hf and Ni; x has a value from 0 to 1; y has a value of 0, 1 or 2; and z has an integer value of 1 through 7. The MOCVD process uses precursors selected from alkoxide precursors, β-diketonate precursors, and metal carbonyl precursors in combination to produce metal-containing films, including resistive memory materials.
摘要翻译：提供了一种用于形成具有通式M 1，X 2，M 1，M 2，M 1，M 2，其中M'是选自La，Ce，Pr，Nd，Pm，Sm，Y，Sc，Yb，Lu和Gd中的金属; M“是选自Mg，Ca，Sr，Ba，Pb，Zn和Cd的金属; M是选自Mn，Ce，V，Fe，Co，Nb，Ta，Cr，Mo，W，Zr，Hf和Ni中的金属; x的值为0到1; y的值为0,1或2; 并且z具有1至7的整数值.MOCVD方法组合使用选自醇盐前体，β-二酮前体和金属羰基前体的前体，以产生包含电阻记忆材料的含金属膜。

5. 发明授权

US06905937B2 Methods of fabricating a cross-point resistor memory array 有权
标题翻译：制造交叉点电阻存储器阵列的方法
公开(公告)号：US06905937B2
公开(公告)日：2005-06-14
申请号：US10391292
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , H01L21/20
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
摘要翻译：提供了电阻式交叉点存储器件，以及制造和使用方法。存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。电阻性交叉点存储器件通过在衬底内掺杂一个极性而形成，然后将相反极性的线的掺杂区域形成二极管。然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

6. 发明授权

US06825058B2 Methods of fabricating trench isolated cross-point memory array 有权
标题翻译：制造沟槽隔离交叉点存储器阵列的方法
公开(公告)号：US06825058B2
公开(公告)日：2004-11-30
申请号：US10391290
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： H01L2100
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
摘要翻译：提供了电阻式交叉点存储器件，以及制造和使用方法。存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。在电阻性存储器材料和下部电极之间的界面处形成二极管，其可以形成为通过浅沟槽隔离彼此隔离的掺杂区域。电阻交叉点存储器件通过在衬底内通过浅沟槽隔离彼此分离的线路形成一个极性，然后将相反极性的线的掺杂区域形成二极管形成。然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

7. 发明授权

US06824814B2 Preparation of LCPMO thin films which have reversible resistance change properties 有权
标题翻译：制备具有可逆电阻变化特性的LCPMO薄膜
公开(公告)号：US06824814B2
公开(公告)日：2004-11-30
申请号：US10153841
申请日：2002-05-21
申请人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan , Masayuki Tajiri
发明人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan , Masayuki Tajiri
IPC分类号： B05D512
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1283 , G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.
摘要翻译：形成钙钛矿薄膜的方法包括制备钙钛矿前体溶液; 制备用于沉积钙钛矿薄膜的硅衬底，包括在衬底上形成底电极; 将基材固定在旋涂装置中并以预定的旋转速率旋转基材; 将钙钛矿前体溶液注入到旋涂装置中，由此用钙钛矿前体溶液涂覆基材以形成涂布的基材; 在从约90℃增加到300℃的温度下烘烤涂覆的基材; 并在约500℃至800℃的温度下退火涂覆的基材5分钟至15分钟。

8. 发明授权

US06774004B1 Nano-scale resistance cross-point memory array 有权
标题翻译：纳米级电阻交叉点存储阵列
公开(公告)号：US06774004B1
公开(公告)日：2004-08-10
申请号：US10391357
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L2120
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

9. 发明授权

US06654210B2 Solid-state inductor and method for same 失效
标题翻译：固态电感及其相同方法
公开(公告)号：US06654210B2
公开(公告)日：2003-11-25
申请号：US10131411
申请日：2002-04-22
申请人： Wei Pan , Sheng Teng Hsu , Wei-Wei Zhuang
发明人： Wei Pan , Sheng Teng Hsu , Wei-Wei Zhuang
IPC分类号： G11B5127
CPC分类号： G11C13/0007 , G11C2213/31 , H01F10/193 , H01F21/00 , H01F41/24 , H01L27/08 , H01L28/10 , Y10T29/4902
摘要： A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; applying an electrical field treatment to the CMR thin film in the range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms); in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; and, in response to the applied bias voltage, creating an inductance between the top and bottom electrodes. When the applied bias voltage is varied, the inductance varies in response.
摘要翻译：提供固态电感器和形成固态电感器的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）薄膜; 形成覆盖CMR薄膜的顶部电极; 以0.1纳秒（ns）至1毫秒（ms）的脉冲宽度在0.4至1兆伏特/厘米（MV / cm）范围内对CMR薄膜进行电场处理; 响应于电场处理，将CMR薄膜转换成CMR薄膜电感器; 在顶部和底部电极之间施加偏置电压; 并且响应于施加的偏置电压，在顶部和底部电极之间产生电感。当施加的偏置电压变化时，电感响应变化。

10. 发明授权

US07157287B2 Method of substrate surface treatment for RRAM thin film deposition 有权
标题翻译： RRAM薄膜沉积的基板表面处理方法
公开(公告)号：US07157287B2
公开(公告)日：2007-01-02
申请号：US10855088
申请日：2004-05-27
申请人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David R. Evans , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1241 , C23C18/1283 , C30B23/02 , C30B29/24 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.
摘要翻译：制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

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