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    • 1. 发明授权
    • High throughput UART to DSP interface having Dual transmit and receive FIFO buffers to support data transfer between a host computer and an attached modem
    • 高吞吐量UART至DSP接口,具有双发送和接收FIFO缓冲器,可支持主机和附加调制解调器之间的数据传输
    • US06381661B1
    • 2002-04-30
    • US09321905
    • 1999-05-28
    • Shayne MesserlyHarrison KillianDavid Arnesen
    • Shayne MesserlyHarrison KillianDavid Arnesen
    • G06F1312
    • G06F13/24G06F13/385
    • The high throughput UART to DSP interface (UDIF) maintains UART functionality while integrating dual Transmit (Tx) and Receive (Rx) FIFO buffers that are optimized for more efficient interaction with their respective I/O processors. The portion of the interface design interacting with the DSP, the UDIF, provides several unique Status, Informational, and Control registers that lower the DSP overhead required for many of the basic modem functions. The UDIF design also performs parity add, parity strip, and character echo functions, traditionally performed at a high overhead cost by the DSP. These functions are more efficiently preformed by hardware implementations than by the software routines executed by the DSP. More burdensome command functions like escape, AT, and flow control commands can also be implemented through hardware implementations to reduce processor overhead.
    • 高吞吐量UART到DSP接口(UDIF)在集成双发送(Tx)和接收(Rx))FIFO缓冲器时保持UART功能,该缓冲器经过优化,可与各自的I / O处理器进行更有效的交互。 接口设计与DSP(UDIF)交互的部分提供了几种独特的状态,信息和控制寄存器,可以降低许多基本调制解调器功能所需的DSP开销。 UDIF设计还执行奇偶校验位,奇偶校验位和字符回波功能,传统上由DSP以高额外的成本执行。 这些功能通过硬件实现更有效地执行,而不是由DSP执行的软件程序执行。 还可以通过硬件实现来实现更加繁重的命令功能,如转义,AT和流控制命令,以减少处理器开销。
    • 8. 发明授权
    • Systems and methods for impedance synthesis
    • 用于阻抗合成的系统和方法
    • US06859051B1
    • 2005-02-22
    • US10452373
    • 2003-06-02
    • Spiro PoulisJohn EvansShayne Messerly
    • Spiro PoulisJohn EvansShayne Messerly
    • H04B1/58G01R27/08H03L5/00H04M1/24
    • H04B1/58
    • The present invention synthesizes a prescribed impedance. The impedance is synthesized by generating a current having a value substantially equal to a voltage divided by a prescribed impedance. Sensing the line voltage and converting that sensed line voltage to its digital equivalent accomplish this first step. The digital line voltage is processed by a factor related to the prescribed impedance to produce an output voltage that has a value substantially equal to the sensed voltage divided by the prescribed impedance. The output voltage controls a voltage to current converter that generates the appropriate current across the points or terminals where the line voltage was measured. Thus, the prescribed impedance is generated across these points or terminals because the line voltage divided by the generated current is substantially equal to the prescribed impedance.
    • 本发明合成规定的阻抗。 通过产生具有基本上等于被规定阻抗除以的电压的值的电流来合成阻抗。 感测线路电压并将感测到的线路电压转换为其数字等效电压完成了第一步。 数字线路电压由与规定阻抗相关的因子处理,以产生具有基本上等于感测电压除以规定阻抗的值的输出电压。 输出电压控制电压到电流转换器,其在测量线路电压的点或端子处产生适当的电流。 因此,由于产生的电流除以的线电压基本上等于规定的阻抗,所以在这些点或端子之间产生规定的阻抗。
    • 9. 发明授权
    • Transfer function implementation using digital impedance synthesis
    • 使用数字阻抗合成的传递函数实现
    • US06338077B1
    • 2002-01-08
    • US09321899
    • 1999-05-28
    • Spiro PoulisJohn EvansShayne Messerly
    • Spiro PoulisJohn EvansShayne Messerly
    • G06J100
    • H03H17/02
    • A system and circuit is provided for digitally synthesizing the impedance of a transfer function. The impedance of the transfer function is digitally synthesized by generating a current that, when combined with an input voltage, results in the impedance of the transfer function. This is accomplished by sensing the input signal and processing it with a generator or multiplier such that a voltage is produced. The produced voltage controls a current source and creates a current having a value equal to the inverse of the transfer function impedance. The sensed or input voltage divided by the generated current is equal to the impedance of the transfer function. In this manner, many different transfer functions can be digitally synthesized without having to design an alternate circuit.
    • 提供了一种用于数字合成传递函数的阻抗的系统和电路。 传递函数的阻抗通过产生与输入电压组合导致传递函数的阻抗的电流数字合成。 这通过感测输入信号并用发生器或乘法器来处理,从而产生电压来实现。 产生的电压控制电流源并产生具有等于传递函数阻抗的倒数的值的电流。 感测或输入电压除以发电电流等于传递函数的阻抗。 以这种方式,可以数字地合成许多不同的传递函数,而不必设计备用电路。
    • 10. 发明授权
    • Methods and apparatus for adaptive filters
    • 自适应滤波器的方法和装置
    • US06308192B1
    • 2001-10-23
    • US09201351
    • 1998-11-30
    • Shayne Messerly
    • Shayne Messerly
    • G06F1710
    • H03H21/0012
    • The present invention relates to improved adaptive filtering techniques and architectures. Preferably, this filtering is performed as part of the digital processing that occurs with a digital signal processor. It is a feature of this invention that the adaptive filtering taught herein provides the advantages of both serial and parallel architectures, without the accompanying disadvantages thereof. In particular, an adaptive filter is taught that possesses low pin counts, fast processing times suitable for high-speed applications and reduced numbers of filter elements. In a preferred embodiment, the inputs and outputs of the adaptive filter are supplied to and from the adaptive filter in a serial manner while the processing is performed internally within the adaptive filter in a parallel manner. The parallel processing is preferably effected by a delayed least-means-squares algorithm implemented using a single adder, a single multiplier and a single multiplier-accumulator instead of by numerous such adders, multipliers and multiplier-accumulators.
    • 本发明涉及改进的自适应滤波技术和架构。 优选地,该滤波作为数字信号处理器发生的数字处理的一部分来执行。 本发明的一个特征是本文教导的自适应滤波器提供了串行和并行架构的优点,而没有其伴随的缺点。 特别地,教导了具有低引脚数,适合于高速应用的快速处理时间和减少数量的滤波器元件的自适应滤波器。 在优选实施例中,自适应滤波器的输入和输出以串行方式提供给自适应滤波器,并且在自适应滤波器内部以并行方式执行处理。 并行处理优选地通过使用单个加法器,单个乘法器和单个乘法器累加器而不是由许多这样的加法器,乘法器和乘法器累加器实现的延迟最小均方算法来实现。