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1. 发明公开

EP1670051A1 Apparatus and method for cvd copper removal at low temperature 审中-公开
标题翻译： Anordnung und Methode zur Entfernung von CVD Kupfer mit nietriger Temperatur
公开(公告)号：EP1670051A1
公开(公告)日：2006-06-14
申请号：EP06075568.3
申请日：1998-10-23
申请人： SHARP KABUSHIKI KAISHA , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Ulrich, Bruce Dale , Nguyen, Tue , Kobayashi, Masato
IPC分类号： H01L21/3213 , C23F1/00
CPC分类号： H01L21/32134 , C23F1/18 , H01L21/02063 , H01L21/02087 , H01L21/3212 , H01L21/6708
摘要： An apparatus for removing copper from semiconductor wafer disk having top and bottom surfaces, with top surface edges and sides along the top surface edge around the perimeter of the wafer surfaces comprises: an enclosed chamber; a spin-chuck to rotate the mounted wafer; a first solution application nozzle having at least one position approximately above the wafer edge to spray diluted copper etchant solution at room temperature towards the sides and perimeter edge of the wafer, to remove copper from the sides and perimeter edge of the wafer; a second nozzle having at least one position approximately above the wafer perimeter to spray a protective coating etchant upon the edge of the wafer top surface along the perimeter, whereby protective coating, masking copper interconnection structures on the wafer top surface, is removed on the edge of the top surface and the wafer side before copper etchant is applied; and a third solution application nozzle having at least one position approximately above the center of the wafer to spray de-ionized water on the wafer, whereby the water is used to remove etchants and etchant compounds from the wafer.
摘要翻译：一种用于从具有顶表面和底表面的半导体晶片盘中去除铜的装置，具有围绕晶片表面的周边的顶表面边缘的顶表面边缘和侧边包括：封闭室; 用于旋转安装的晶片的旋转卡盘; 第一溶液施加喷嘴，其具有大约在晶片边缘上方的至少一个位置，以在室温下朝向晶片的侧面和周边边缘喷射稀释的铜蚀刻剂溶液，以从晶片的侧面和周边边缘移除铜; 第二喷嘴具有大约在晶片周边上方的至少一个位置，以沿着周边在晶片顶表面的边缘上喷射保护性涂层蚀刻剂，由此在晶片顶表面上的保护涂层，掩模铜互连结构在边缘上被去除在施加铜蚀刻剂之前的顶表面和晶片侧; 以及第三溶液施加喷嘴，其具有大约高于晶片中心的至少一个位置以在晶片上喷射去离子水，由此使用水从晶片去除蚀刻剂和蚀刻剂化合物。

2. 发明公开

EP1246253A2 MFMOS transistor memory structures with high dielectric constant materials and a method of making the same 审中-公开
标题翻译： MFMOS存储器具有高介电常数的材料的晶体管结构，并且这种效果的制造方法
公开(公告)号：EP1246253A2
公开(公告)日：2002-10-02
申请号：EP02006896.1
申请日：2002-03-26
申请人： Sharp Kabushiki Kaisha
发明人： Li, Tingkai , Hsu, Sheng Teng , Ying, Hong , Ulrich, Bruce Dale , Ma, Yanjun
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO 2 , HfO 2 , Y 2 O 3 , or La 2 O 3 , or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.
摘要翻译：为铁电非易失性存储器中的一个MFMOS一个晶体管存储器结构包括高介电常数材料：例如ZrO 2，的HfO 2，Y 2 O 3，或镧，或类似物，或它们的混合物，以减少操作电压，并且增加内存窗口和装置的可靠性。

3. 发明公开

EP1308993A3 High-K gate oxides with buffer layers of titanium for mfos single transistor memory applications 审中-公开
标题翻译：有用于MFOH单晶体管存储器应用钛缓冲层Hochdielektrizitätszahl栅氧化物
公开(公告)号：EP1308993A3
公开(公告)日：2007-11-07
申请号：EP02024051.1
申请日：2002-10-28
申请人： Sharp Kabushiki Kaisha
发明人： Li, Tingkai , Hsu, Sheng Teng , Ulrich, Bruce Dale , Horn Stecker, Lisa
IPC分类号： H01L21/28 , H01L29/78 , H01L29/51 , H01L21/316 , C23C16/02 , C23C16/40 , C23C16/56 , H01L29/40
CPC分类号： H01L21/28185 , C23C16/0272 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/3144 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/56 , H01L29/40 , H01L29/513 , H01L29/516 , H01L29/517
摘要： A method of fabricating a memory device includes preparing a silicon substrate; depositing a layer of high-k insulator on the silicon substrate; depositing a buffering layer on the high-k insulating layer; depositing a layer of ferroelectric material on the buffering layer by metal organic chemical vapor deposition; forming a top electrode on the layer of ferroelectric material; and completing the device obtained by above steps.

4. 发明公开

EP0924754A2 Low temperature system and method for CVD copper removal 审中-公开
标题翻译： Anordnung und Methode zur Entfernung von CVD Kupfer mit nietriger Temperatur
公开(公告)号：EP0924754A2
公开(公告)日：1999-06-23
申请号：EP98308687.7
申请日：1998-10-23
申请人： Sharp Kabushiki Kaisha , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Ulrich, Bruce Dale , Nguyen, Tue , Kobayashi, Masato
IPC分类号： H01L21/3213 , C23F1/00
CPC分类号： H01L21/32134 , C23F1/18 , H01L21/02063 , H01L21/02087 , H01L21/3212 , H01L21/6708
摘要： A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one method, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied In another method, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third method, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.
摘要翻译：在半导体晶片的制造中，从晶片上去除铜的方法包括在包括铜互连的晶片顶表面上的选定区域上形成一层保护涂层。蚀刻保护涂层以将其从晶片的顶表面和侧面的边缘移除，而不是从顶部表面铜互连。稀释铜蚀刻剂溶液在室温下使用以从未被保护涂层覆盖的部分去除铜。晶片包括至少一个直的顶表面边缘和侧面，并且保护涂层是沉积在晶片顶表面上的光致抗蚀剂。沿着直的顶边缘表面的光致抗蚀剂的选定区域通过靠近晶片的荫罩曝光，以化学改变曝光的光致抗蚀剂。光致抗蚀剂被显影以沿着顶表面的直边缘去除它，随后从顶表面直边蚀刻铜。用去离子水冲洗将晶片清除铜蚀刻剂化合物，并将蚀刻的保护涂层从晶片上完全除去。在替代实施例中：（i）当应用铜蚀刻剂时，晶片的敏感区域可以用喷水器保护; （ii）在对沉积的铜层进行化学机械抛光之前，施加铜蚀刻剂以清除铜的晶片周边，其中Coper的过剩厚度保护铜互连结构不与铜蚀刻剂反应。另一种保护涂层是旋涂玻璃。

5. 发明公开

EP1189110A2 Method of making a multi-level reticle using bi-level photoresist, including a phase-shiffed multi-level reticle 审中-公开
标题翻译：用于通过两层抗蚀剂的装置制造多层光掩模方法和相移掩模的多层
公开(公告)号：EP1189110A2
公开(公告)日：2002-03-20
申请号：EP01307845.6
申请日：2001-09-14
申请人： SHARP KABUSHIKI KAISHA
发明人： Ulrich, Bruce Dale , Maliszewski, Gerald William
IPC分类号： G03F1/00 , G03F1/14
CPC分类号： G03F1/32 , G03F1/28
摘要： A method of forming a reticle includes providing a reticle blank having a quartz layer, an attenuated phase shift layer, and a metal layer, covering the reticle blank with resist ; patterning the resist into multiple levels; and etching the reticle blank according to the multi-level resist : pattern.
摘要翻译：形成掩模版的方法包括：提供掩模母版坯料具有石英层，以衰减相移层和金属层，覆盖抗蚀剂掩模版坯料; 图案化该抗蚀剂为多个电平; 以及蚀刻所述掩模版空白gemäß到所述多级的抗蚀剂：图案。

6. 发明公开

EP0924754A3 Low temperature system and method for CVD copper removal 审中-公开
标题翻译：用于CVD铜去除的低温系统和方法
公开(公告)号：EP0924754A3
公开(公告)日：1999-09-08
申请号：EP98308687.7
申请日：1998-10-23
申请人： Sharp Kabushiki Kaisha , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Ulrich, Bruce Dale , Nguyen, Tue , Kobayashi, Masato
IPC分类号： H01L21/3213 , C23F1/00
CPC分类号： H01L21/32134 , C23F1/18 , H01L21/02063 , H01L21/02087 , H01L21/3212 , H01L21/6708
摘要： A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one method, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied In another method, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third method, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.
摘要翻译：提供了使用稀释硝酸和边缘珠去除工具从半导体晶片的周边去除铜的方法。在一种方法中，在施加酸之前，晶片的敏感区域覆盖有光致抗蚀剂，并且晶片周边清除了光致抗蚀剂。在另一种方法中，当施加铜蚀刻剂时，晶片的敏感区域用喷水保护。在第三种方法中，在对沉积的铜层执行化学机械抛光（CMP）之前，施加硝酸以清除铜的晶圆周边。铜的多余厚度保护铜互连结构免于与铜蚀刻剂反应。所有这些方法都允许在足够低的温度下去除铜，以致不会形成铜氧化物。还提供了根据上述方法清除铜的半导体晶片以及用于低温铜去除的系统。

7. 发明公开

EP1353369A2 Method for producing semiconductor device 有权
标题翻译：生产半导体器件的方法
公开(公告)号：EP1353369A2
公开(公告)日：2003-10-15
申请号：EP03251430.9
申请日：2003-03-10
申请人： SHARP KABUSHIKI KAISHA
发明人： Evans, David Russell , Hsu, Sheng Teng , Ulrich, Bruce Dale , Tweet, Douglas James , Stecker, Lisa H.
IPC分类号： H01L21/762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975
摘要： The present invention provides a method for producing a semiconductor device using a self-aligned shallow trench isolation process isolating elements formed so as to be self-aligned to a gate structure, the method comprising the steps of: providing a first polysilicon layer overlying a gate insulator layer on a substrate; forming a trench through the first polysilicon layer, and into the substrate; providing an oxide layer overlying the substrate including the trench such that a top surface of the oxide layer within the trench is higher than a bottom surface of the first polysilicon layer; providing a second polysilicon layer overlying the oxide layer such that a top surface of the second polysilicon layer within the trench is lower than the top surface of the first polysilicon layer; and planarizing the second polysilicon layer, the oxide layer, and the first polysilicon layer, while stopping the step of planarizing at the top surface of the second polysilicon layer within the trench.
摘要翻译：本发明提供一种使用自对准浅沟槽隔离工艺来制造半导体器件的方法，所述半导体器件形成为与栅极结构自对准地形成，所述方法包括以下步骤：提供覆盖栅极的第一多晶硅层衬底上的绝缘体层; 穿过第一多晶硅层形成沟槽并进入衬底; 提供覆盖包括沟槽的衬底的氧化物层，使得沟槽内的氧化物层的顶表面高于第一多晶硅层的底表面; 提供覆盖所述氧化物层的第二多晶硅层，使得所述沟槽内的所述第二多晶硅层的顶表面低于所述第一多晶硅层的顶表面; 以及平坦化第二多晶硅层，氧化物层和第一多晶硅层，同时停止在沟槽内的第二多晶硅层的顶表面处进行平坦化的步骤。

8. 发明公开

EP1189110A3 Method of making a multi-level reticle using bi-level photoresist, including a phase-shiffed multi-level reticle 审中-公开
标题翻译：用于通过两层抗蚀剂的装置制造多层光掩模方法和相移掩模的多层
公开(公告)号：EP1189110A3
公开(公告)日：2002-08-28
申请号：EP01307845.6
申请日：2001-09-14
申请人： SHARP KABUSHIKI KAISHA
发明人： Ulrich, Bruce Dale , Maliszewski, Gerald William
IPC分类号： G03F1/00 , G03F1/14
CPC分类号： G03F1/32 , G03F1/28
摘要： A method of forming a reticle includes providing a reticle blank having a quartz layer, an attenuated phase shift layer, and a metal layer, covering the reticle blank with resist ; patterning the resist into multiple levels; and etching the reticle blank according to the multi-level resist : pattern.

9. 发明授权

EP1353369B1 Method for producing semiconductor device 有权
公开(公告)号：EP1353369B1
公开(公告)日：2007-12-12
申请号：EP03251430.9
申请日：2003-03-10
申请人： Sharp Kabushiki Kaisha
发明人： Evans, David Russell , Hsu, Sheng Teng , Ulrich, Bruce Dale , Tweet, Douglas James , Stecker, Lisa H.
IPC分类号： H01L21/762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975

10. 发明公开

EP1246253A3 MFMOS transistor memory structures with high dielectric constant materials and a method of making the same 审中-公开
标题翻译： MFMOS存储器具有高介电常数的材料的晶体管结构，并且这种效果的制造方法
公开(公告)号：EP1246253A3
公开(公告)日：2004-10-13
申请号：EP02006896.1
申请日：2002-03-26
申请人： Sharp Kabushiki Kaisha
发明人： Li, Tingkai , Hsu, Sheng Teng , Ying, Hong , Ulrich, Bruce Dale , Ma, Yanjun
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO 2 , HfO 2 , Y 2 O 3 , or La 2 O 3 , or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

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