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1. 发明授权

EP1458026B1 Low temperature processing of PCMO thin film on an Iridium layer for RRAM application 有权
标题翻译：低温工艺用于RRAM应用铱层上产生PCMO薄膜
公开(公告)号：EP1458026B1
公开(公告)日：2008-11-26
申请号：EP04250772.3
申请日：2004-02-12
申请人： Sharp Kabushiki Kaisha
发明人： Zhang, Fengyan , Zhuang, Weiwei , Pan, Wei , Hsu, Sheng Teng
IPC分类号： H01L27/10
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608

2. 发明授权

EP1469519B1 1R1D R-RAM array with floating P-well 有权转让
标题翻译： 1R1D R-RAM阵列与隔离P阱
公开(公告)号：EP1469519B1
公开(公告)日：2008-11-19
申请号：EP04250897.8
申请日：2004-02-19
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei , Zhang, Fengyan
IPC分类号： H01L27/10 , H01L27/24
CPC分类号： H01L27/24 , G11C13/0007 , G11C2213/31 , G11C2213/72 , H01L27/10

3. 发明授权

EP1035588B1 Iridium conductive electrode/barrier structure and method for same 有权
标题翻译：用于制备由铱和阻挡结构和方法的导电电极
公开(公告)号：EP1035588B1
公开(公告)日：2008-05-07
申请号：EP00301789.4
申请日：2000-03-06
申请人： Sharp Kabushiki Kaisha , Sharp Laboratories of America, Inc.
发明人： Zhang, Fengyan , Maa, Jer-Shen , Hsu, Sheng Teng
IPC分类号： H01L29/45 , H01L21/28
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65

4. 发明授权

EP1353369B1 Method for producing semiconductor device 有权
公开(公告)号：EP1353369B1
公开(公告)日：2007-12-12
申请号：EP03251430.9
申请日：2003-03-10
申请人： Sharp Kabushiki Kaisha
发明人： Evans, David Russell , Hsu, Sheng Teng , Ulrich, Bruce Dale , Tweet, Douglas James , Stecker, Lisa H.
IPC分类号： H01L21/762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975

5. 发明公开

EP1458026A3 Low temperature processing of PCMO thin film on ir substrate for rram application 有权
标题翻译：低温工艺用于RRAM应用IR在基底上产生一个PCMO薄膜
公开(公告)号：EP1458026A3
公开(公告)日：2006-07-26
申请号：EP04250772.3
申请日：2004-02-12
申请人： SHARP KABUSHIKI KAISHA
发明人： Zhang, Fengyan , Zhuang, Weiwei , Pan, Wei , Hsu, Sheng Teng
IPC分类号： H01L27/10
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the layer of iridium; baking the layer of PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the layer of PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the layer of PCMO has a desired thickness; annealing the substrate and the layer of PCMO; depositing a top electrode; and completing the RRAM device.

6. 发明授权

EP1320125B1 Seed layer processes for mocvd of ferroelectric thin films on high-K gate oxides 有权
标题翻译：一种用于形成籽晶层用于生产铁电薄膜的通过MOCVD在栅极氧化物高的介电常数的方法
公开(公告)号：EP1320125B1
公开(公告)日：2006-04-26
申请号：EP02024963.7
申请日：2002-11-07
申请人： SHARP KABUSHIKI KAISHA
发明人： Li, Tingkai , Hsu, Sheng Teng
IPC分类号： C23C16/00 , H01L21/28
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517

7. 发明公开

EP1643000A1 Seed layer processes for MOCVD of ferroelectric thin films on high-K gate oxides 审中-公开
标题翻译： MOCVD方法在栅极氧化物形成晶种层用于生产ferroelekrischer层高Dielektizitätkonstanten
公开(公告)号：EP1643000A1
公开(公告)日：2006-04-05
申请号：EP06000295.3
申请日：2002-11-07
申请人： SHARP KABUSHIKI KAISHA
发明人： Li, Tingkai , Hsu, Sheng Teng
IPC分类号： C23C16/00 , H01L21/28
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.
摘要翻译：形成的高k层上的铁电薄膜的方法包括：制备硅衬底; 形成在衬底上的高k层; 在高k层上的相对高的温度淀积铁电材料的籽晶层; 沉积在相对低的温度下的晶种层上的铁电材料的顶层; 和退火该基底，该高k层和强电介质层，以形成铁电薄膜。

8. 发明授权

EP0999597B1 Ferroelectric nonvolatile transistor and method of making same 有权
标题翻译：一种铁电非易失性晶体管及其制造方法
公开(公告)号：EP0999597B1
公开(公告)日：2006-01-18
申请号：EP99307192.7
申请日：1999-09-10
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Zhang, Fengyang , Maa, Jer-shen , Li, Tingkai
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/6684 , H01L29/78391

9. 发明公开

EP1150353A3 Using lightly doped resistor for output stage electrostatic discharge protection 审中-公开
标题翻译：针对功率放大器的静电放电保护使用leichtdotiertem电阻的
公开(公告)号：EP1150353A3
公开(公告)日：2005-09-21
申请号：EP01303801.3
申请日：2001-04-26
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng
IPC分类号： H01L27/02 , H01L21/8238
CPC分类号： H01L21/823807 , H01L27/0288
摘要： A method of fabricating a CMOS device having improved electrostatic discharge protection properties includes preparing a silicon substrate; forming an n-well for a pMOS active region; forming a p-well for an nMOS active region; and implanting ions to form a lightly doped drain series resistor in at least on of the active regions. An electrostatic discharge protection structure for use in a CMOS device having a pMOST and an nMOST therein includes an electrostatic triggering structure to uniformly trigger both pMOST and nMOST output to protect against positive and negative electrostatic discharge events.

10. 发明公开

EP1469519A2 1R1D R-ram array with floating P-well 有权转让
标题翻译： 1R1D R-RAM-Zellenfeld mit schwebender P-Wanne
公开(公告)号：EP1469519A2
公开(公告)日：2004-10-20
申请号：EP04250897.8
申请日：2004-02-19
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei , Zhang, Fengyan
IPC分类号： H01L27/10
CPC分类号： H01L27/24 , G11C13/0007 , G11C2213/31 , G11C2213/72 , H01L27/10
摘要： A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate (202); forming an n-doped buried layer (buried n layer) (204) of silicon overlying the substrate; forming n-doped silicon sidewalls (210) overlying the buried n layer; forming a p-doped well of silicon (p-well) (206) overlying the buried n layer; and, forming a 1R1D R-RAM array (208) overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls (212), and the method further comprises: forming an oxide insulator (214) overlying the p-well sidewalls, between the n-well and the R-RAM array.
摘要翻译：提供具有浮动p-well的低电容单电阻/单二极管（1R1D）R-RAM阵列。该制造方法包括：形成集成电路（IC）衬底（202）; 形成覆盖在衬底上的硅的n掺杂掩埋层（掩埋n层）（204）; 形成覆盖所述掩埋n层的n掺杂硅侧壁（210）; 形成覆盖在掩埋n层上的硅（p阱）（206）的p掺杂阱; 并且形成覆盖p阱的1R1D R-RAM阵列（208）。通常，掩埋n层和n掺杂侧壁的组合形成硅的n掺杂阱（n阱）。然后，p阱形成在n阱内。在其它方面，p阱具有侧壁（212），并且该方法还包括：形成覆盖p阱侧壁，n阱和R-RAM阵列之间的氧化物绝缘体（214）。

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